This paper proposes a high-frequency integrated gate driver for gallium nitride (GaN) synchronous buck converter. The proposed adaptive bang-bang dead-time control minimizes dead-time at any load condition. Thus, it mitigates the excessive power loss caused by GaN device reverse conduction in high-frequency applications. The proposed charge sharing bootstrap circuit ensures sufficient gate overdrive voltage with reduced chip area. Fabricated in a TSMC 0.25-m BCD process, the driver integrated circuit (IC) enabled GaN-based buck converter to operate at 10 MHz switching frequency with minimal dead-time to as low as 0.4 ns under light load and heavy load conditions. Compared with fixed dead-time control, the proposed work improves around 5% efficiency under heavy load condition. The fully integrated bootstrap circuit with 100 pF and 60 pF (HV) capacitor obtained the lower than 0.6 V driving voltage drop with only 45% capacitance and around half of the voltage drop compared to a conventional bootstrap circuit. Besides, the proposed driver successfully tackled the parasitic ringing and dead-time overcharging issues in the GaN converter.

This brief proposes a driver integrated circuit (IC) for a GaN-based synchronous buck converter to minimized the dead-time loss of GaN devices and improve converter efficiency. The proposed adaptive control achieves minimized dead-time for any loading condition. A driver IC is fabricated in a 0.18 ${\mu }\text{m}$ BCD process to verify the concept. The measurement result achieves only 0.7 ns and 0.8 ns dead-time at the minimum and maximum load condition, respectively. The efficiency improves 2.1% at 2 A full load compared to the fixed dead-time control counterpart.

Flyback converter with USB power delivery is widely used for fast-charging mobile devices. However, conventional solutions have issues such as lower efficiency, higher cost, a large number of external components, and lower loop gain bandwidth. In this article, a high-efficiency zero-voltage switching (ZVS) flyback converter with primary- and secondary-side control ICs is proposed to solve the aforementioned issues with high integration level. The proposed control replaces optocoupler to achieve ZVS and secondary-side-regulation (SSR) by a pulse transformer. The ICs further integrate the USB power delivery (PD) controller and the constant voltage (CV)/constant current (CC) loop compensation to reduce external components. The proposed control and small-signal model are illustrated and verified by the experiment. The control ICs were fabricated in a 180-nm BCD process. The implemented 20-V/3-A/60-W USB PD flyback converter achieved 93.5% maximum efficiency using Si power switches. The feasibility of the proposed converter is verified by a thorough test of programmable power supply (PPS) with various CC/CV levels and load/line transients.

With the rapid advancement of artificial intelligence (AI) in mobile devices, power supply requirements such as fast transient response and high light-load efficiency for processors are increasingly critical. In this article, a double capacitor current ramp integrating constant on-time (DCCRICOT) control is proposed to achieve an ultrafast load transient response and a high noise immunity over other control schemes. Conventional control schemes with capacitor current sensing ensure an ultra-fast load transient response but suffer from sensing circuit mismatch-induced instability. Hence, a double capacitor current ramp integrating scheme is proposed to provide stable operation without sacrificing load transient response. Moreover, this scheme improves noise immunity, providing accurate triggers in both continuous-conduction mode (CCM) and discontinuous-conduction mode (DCM). Implemented in a 0.18 μm CMOS process, this chip size is 1289 μm by 1199 μm. Experimental results demonstrate a fast load transient response with a 62 mV near optimal output voltage drop (deviation-from-ideal rate is only 1.9%) and a 1.6 μs response time without any instability issue under conditions of a 1.1 A load step-up with a 1.1 A/70 ns slew rate.

This paper proposed a switching behavior equivalent circuit model for the gate driver board of SiC MOSFETs that includes the gate driver IC and parasitic components of the printed circuit board (PCB). Because SiC applications involve high switching frequency, high voltages, and high currents, the gate driver would greatly affect the switching performance and loss. Therefore, this paper presents a novel equivalent circuit model for SiC gate driver that incorporates nonlinear resistors and capacitors of driver output stage and parasitic inductance of PCB to achieve a more accurate prediction of switching behavior. The equivalent circuit model is then built into LTSPICE simulation model and compared with measured VGS waveform of gate driver board connected to a capacitor to model the input capacitance of SiC. Compared with the old modeling methods, the new modeling methods reduces the error between the simulation and measurement for $\mathrm{V}_{\mathrm{o}\mathrm{u}\mathrm{t}}$ rising (falling) time from 15% to less than 1%. The accurate equivalent circuit can provide accurate digital twin and help designers reduce testing time and cost.

Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This paper proposes an event-driven self-clocked DLDO regulator. The proposed low quiescent current (I_Q) event-driven adaptive frequency clock generator (EACG) adapts its frequency in different load conditions without a current sensor or complex compensation circuit for stable operation in the entire load range. The proposed DLDO does not need any external clocking signal and can maintain low output ripple and low power consumption in the steady-state. The clock-less transient detector (CLTD), consisting of two clock-independent transient detection paths, uses power more efficiently and improves the transient response significantly without sacrificing the power consumption. This work was fabricated in a 40 nm CMOS process with an 0.3 nF on-chip capacitor. The measurement results show that with the step load current between 1 mA and 60 mA, the proposed DLDO achieves a transient recovery time of 220 ns. The total I_Q of the proposed DLDO is only 26 μA in steady-state, and it achieves stable operation in the entire load range.