In this manuscript, we present a survey of designs and implementations of research sensor nodes that rely on FPGAs, either based upon standalone platforms or as a combination of microcontroller and FPGA. Several current challenges in sensor networks are distinguished and linked to the features of modern FPGAs. As it turns out, low-power optimized FPGAs are able to enhance the computation of several types of algorithms in terms of speed and power consumption in comparison to microcontrollers of commercial sensor nodes. We show that architectures based on the combination of microcontrollers and FPGA can play a key role in the future of sensor networks, in fields where processing capabilities such as strong cryptography, self-testing and data compression, among others, are paramount.

Wireless Sensor Networks (WSNs) have permeated the entire fabric of academic disciplines that greatly rely on control and decision-making processes such as medical health care, agriculture, ecology and industrial automation. In ecology, an infrastructure consisting of networks of interconnected sensors can provide in-situ high-precision monitoring of natural phenomena at a large-scale. Moreover, WSNs provide a number of advantages to ecoinformatics such as the possibility of constructing quality datasets that coupled to machine learning-based prediction systems, can be used for ecological and process modelling. In this manuscript, we present a survey on recent WSNs based on several fields related to environmental research e.g. ecoinformatics, precision agriculture and wildlife observation. Finally, we have focused on the identification of limitations and open problems therein.

Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4–12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires a huge amount of time. In this respect, the required energy consumption can be higher than using a separate accelerator based on a Field-programmable Gate Array (FPGA) that is switched on when needed. In this manuscript, we present the design of a cryptographic accelerator suitable for an FPGA-based sensor node and compliant with the IEEE802.15.4 standard. All the embedded resources of the target platform (Xilinx Artix-7) have been maximized in order to provide a cost-effective solution. Moreover, we have added key negotiation capabilities to the IEEE 802.15.4 security suite based on Elliptic Curve Cryptography (ECC). Our results suggest that tailored accelerators based on FPGA can behave better in terms of energy than contemporary software solutions for motes, such as the TinyECC and NanoECC libraries. In this regard, a point multiplication (PM) can be performed between 8.58- and 15.4-times faster, 3.40- to 23.59-times faster (Elliptic Curve Diffie-Hellman, ECDH) and between 5.45- and 34.26-times faster (Elliptic Curve Integrated Encryption Scheme, ECIES). Moreover, the energy consumption was also improved with a factor of 8.96 (PM).

In the last years, a number of research sensor nodes based on the combination of low-power microcontrollers and FPGAs have been proposed. In these platforms, the FPGAs serve as accelerators of complex algorithms, making it possible to process a vast amount of sensing data in real time. In medical applications that rely on sensors, both privacy and security are of utmost importance. However, the execution of cryptographic primitives on nodes solely based upon microcontrollers clocked at a low frequency can affect the overall power consumption of the platform. In this manuscript, we present the design of a cryptographic accelerator based on FPGA and aimed to be coupled to a microcontroller. It provides the most secure implementation of the IEEE 802.15.4 security suite together with an Elliptic Curve Cryptography (ECC) engine to perform key establishment. Furthermore, we provide a comparison on performance and energy consumption of cryptographic primitives in commercial nodes and in the proposed design. Our results suggest that the controlled execution of cryptographic algorithms on FPGAs clocked at a low frequency improves the performance and energy consumption of the state-of-the-art implementations based on the MICA and Tmote nodes. However, our results also reflect two inherent limitations of this type of design: the very nature of the bus logic can undermine the expected improvement on performance as well as the communication link between the microcontroller and the FPGA can make the platform vulnerable to physical attacks.