Spiking neural networks (SNNs) have attracted considerable attention as third-generation artificial neural networks, known for their powerful, intelligent features and energy-efficiency advantages. These characteristics render them ideally suited for edge computing scenarios. Nevertheless, the current mapping schemes for deploying SNNs onto neuromorphic hardware face limitations such as extended execution times, low throughput, and insufficient consideration of energy consumption and connectivity, which undermine their suitability for edge computing applications. To address these challenges, we introduce EdgeMap, an optimized mapping toolchain specifically designed for deploying SNNs onto edge devices without compromising performance. EdgeMap consists of two main stages. The first stage involves partitioning the SNN graph into small neuron clusters based on the streaming graph partition algorithm, with the sizes of neuron clusters limited by the physical neuron cores. In the subsequent mapping stage, we adopt a multi-objective optimization algorithm specifically geared towards mitigating energy costs and communication costs for efficient deployment. EdgeMap—evaluated across four typical SNN applications—substantially outperforms other state-of-the-art mapping schemes. The performance improvements include a reduction in average latency by up to 19.8%, energy consumption by 57%, and communication cost by 58%. Moreover, EdgeMap exhibits an impressive enhancement in execution time by a factor of 1225.44×, alongside a throughput increase of up to 4.02×. These results highlight EdgeMap’s efficiency and effectiveness, emphasizing its utility for deploying SNN applications in edge computing scenarios.

3D time-of-flight (ToF) cameras have recently attracted widespread attention because of their potential in wide applications. However, the lack of versatile 3D image signal processor (ISP) is still an obstacle that hinders their popularity. The main challenges lie in the management of high-throughput raw data and the complexity of 3D image processing in hardware. To address these challenges, this paper presents a top-down 3D ISP with high real-time performance and high energy efficiency for indirect ToF (IToF) imaging. First, we propose configurable cache strategies to improve the efficiency of non-streaming memory accesses and support different IToF sensors. Then, to resolve the phase ambiguity problem commonly existing in IToF sensors, we develop a hardware-optimized cascaded multi-frequency fusion method, which not only supports up to six modulation frequencies but also facilitates the pixel-wise detection of multipath interference. Moreover, we propose a scalable calculation engine for depth calculation and calibration, 3D image enhancement, and post-processing. The pipeline is prototyped on a Xilinx ZCU102 FPGA board. Results show that the 3D ISP has negligible precision loss and low latency, achieving $53.35\times $ energy efficiency improvement compared with the implementation on Intel CPU and $55.45\times $ improvement over the ARM CPU implementation. When running at 75 MHz, the 3D ISP can support $1280\times 960$ depth, intensity, and point cloud output at a frame rate of 30 f/s.

Spiking neural networks (SNNs) are recognized as the third generation of neural networks, boasting remarkable computational capabilities, which also require massive computational resources and flexibility to simulate biological neural functions. In this work, we present SFANC, a scalable and flexible neuromorphic architecture for SNNs based on optimized router architecture of network-on-chip (NoC) and highly programmable neuromorphic cores (NCs). SFANC includes 16 NCs, supporting 8000 neurons and four million synapses. The NCs are based on RISC-V with SNN-specific instructions, providing remarkable flexibility and computational speed. The NoC’s spiking routers facilitate multicast routing, flow estimation, and buffer sharing, contributing to increased scalability. Additionally, we propose a spectral cluster mapping approach for efficiently deploying SNNs onto SFANC, ensuring high flexibility and parallelism. We analyze the processing speedup for typical SNN topologies using the leaky-integrate-and-fire (LIF) neuron model within the NCs, achieving up to an $8.6\times $ speedup over the RISC-V core on average under different SNN applications. Our enhanced spiking router demonstrates a spike latency reduction of up to 47.4% under various spiking coding schemes. Moreover, when applied to typical SNN topologies, our method exhibits an average spike latency decrease of up to 32.5% compared to the sequential mapping utilized by SpiNNaker. In summary, this work demonstrates high performance, flexibility, and scalability for simulating and accelerating SNNs, showcasing its potential as a promising solution for neuromorphic architectures.