The Energy hole problem, a common phenomenon in wireless sensor networks, significantly decreases the lifetime of any deployed network. Some of the popular techniques to minimize such problems are using mobile sinks instead of static sinks, extending the transmission range dynamically, and deploying redundant sensor nodes near the base station/sink. The major drawback to these techniques are that energy holes may still be created at some point due to their static nature of deployment, despite having the overall residual energy very high. In this research work, we adopt a new approach by dividing the whole network into equiangular wedges and merging a wedge with its neighboring wedge dynamically whenever individual residual energy of all member nodes of a wedge fall below a threshold value. We also propose an efficient Head Node (HN) selection scheme to reduce the transmission energy needed for forwarding data packets among Head Nodes. Simulation results show that WEMER, our proposed WEdge MERging based scheme, provides significantly higher lifetime and better energy efficiency compared to state-of-the-art Power-Efficient Gathering in Sensor Information Systems (PEGASIS) and contemporary Concentric Clustering Scheme (CCS), and Multilayer Cluster Designing Algorithm (MCDA).

Perimeter-gated single-photon avalanche diodes (PGSPADs) have been shown to mitigate premature edge breakdown without unduly increasing the area of the device. PGSPADs are three terminal devices. In this paper, we develop a probability-based SPICE model for the PGSPAD and fully characterize an $18 \times 18$ pixel analog PGSPAD-based CMOS silicon photomultiplier (SiPM). The noise model is derived using theories of carrier thermal generation, carrier diffusion, and inter-band tunneling. Parameters are derived using fabricated PGSPAD devices and model validity is verified with experimental measurements. The designed PGSPAD SiPM is implemented in standard $0.5~\mu \text{m}$ 2-poly, 3-metal CMOS process, and is characterized for dark current, sensitivity, and signal-to-noise ratio (SNR) throughout the visible spectral range for varying bias voltages. Models show that the reduction of dark events in the PGPSAD is primarily caused by a reduction in band-to-band tunneling. Thus, as a function of the applied gate voltage the PGPSAD shows an improvement of SNR over a range of 1 to 1150. The sensitivity of the presented SiPM is $1.06 \times 10^{3}$ A/W/cm ² . The designed PGSPAD SiPM shows great promise over standard SiPM for applications, such as neutron detection which requires high sensitivities and high SNRs.

Application of machine learning (ML) approaches has recently expanded within a wide range of domains, including semiconductor devices. Their strong potential resulted in increasing number of research in semiconductor device modeling and simulation. This article provides a comprehensive review of the recent research on ML-based semiconductor device modeling and simulations. We organize the literature based on the device category, such as Planar Metal–Oxide–Semiconductor (MOS) device, Field-Effect Transistors (FET) devices, High Electron Mobility Transistor (HEMTs) devices and other semiconductor devices. We discuss the implementation of ML methodologies on each device along with the primary findings and summarize them in a Table. This review finds the use of a wide variety of ML approaches in device modeling and simulation, including traditional and deep learning (DL) models. Furthermore, this study shows the ability ofMLmodels to capture the complex, nonlinear patterns in device simulation. Finally, we identify key challenges associated with implementing ML approaches in device simulations and suggest future directions for implementing ML models efficiently. Overall, this review provides useful resources for researchers, engineers, and industry experts interested in leveraging machine learning algorithms to efficiently model semiconductor devices.

This paper presents a new scalable 8 × 8 single photon avalanche diode (SPAD) based vision sensor with integrated spiking neuromorphic system on a single chip. The proposed vision sensing system adopts the benefits of SPAD’s high quantum efficiency and energy efficiency of memristive spiking neuromorphic processing. The SPAD based vision sensor includes biologically inspired address event representation (AER) readout to generate asynchronous digital address events at the output reducing computation and making it suitable to process directly with integrated on-chip spiking neuromorphic system in a faster and more energy efficient way. A novel on-chip interface is designed to convert the output events of a SPAD-based event sensor into temporally coded spikes (TCS) that enable on-chip processing with integrated spiking neuromorphic system. We have tested the prototype vision sensing system for imaging characters by SPAD based vision sensor and recognizing them using the integrated memristive spiking neuromorphic system. To help with the evaluation, we have built a complete temporal pulses data set from simulating the SPAD vision sensor with AER readout in imaging characters and applied directly to integrated spiking neuromorphic system via designed novel on-chip interface. The achieved accuracy is 89.54% with a power consumption of 316 μW for the memristive neuromorphic processor. The SPAD based vision sensor exhibits array-level dynamic range of 148 dB with a power consumption of 2.8mW. The designed SPAD-based vision sensing system with an integrated spiking neuromorphic system on a single chip shows great promise for robotics, autonomous vehicles, health, and security applications.

Neuromorphic computing has become an attractive candidate for emerging computing platforms. It requires an architectural perspective, meaning the topology or hyperparameters of a neural network is key to realizing sound accuracy and performance in neural networks. However, these network architectures must be executed on some form of computer processor. For machine learning, this is often done with conventional computer processing units, graphics processor units, or some combination thereof. A neuromorphic computer processor or neuroprocessor, in the context of this paper, is a hardware system that has been designed and optimized for executing neural networks of one flavor or another. Here, we review the history of neuromorphic computing and consider various spiking neuroprocessor designs that have emerged over the years. The aim of this paper is to identify emerging trends and techniques in the design of such brain-inspired neuroprocessor computer systems.