This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (V _BE ), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz.

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm² and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4.

This paper introduces a broadband linear driver used in B-PLC system. The driver consists of two identical current-feedback amplifiers to realize a fully differential topology. A cross-current injection method between the noninverting and the inverting channels is proposed to reduce the even-order harmonics caused by the circuit mismatch. In addition, in order to increase the stability of the GBW to the changing load and maximize the bandwidth, a output stage implemented by a unit gain closed-loop amplifier is proposed to stabilize the open-loop gain of the overall circuit, meanwhile improve the linearity deteriorated by the crossover distortion. The proposed linear driver is fabricated in a SOI CBJT process and it can provide a maximum drive current of 500 mA under a 12-V power supply. The measurement results show that this linear driver is capable of driving a load of $50~\Omega $ while achieving a output swing of $16~{V_{pp}}$ with a second-order harmonic distortion (HD₂) of −72 dBm and a third-order harmonic distortion (HD₃) of −55 dBm. The bandwidth can reach 120 MHz. A complete in-system measurement also has been passed and the results show that the proposed driver chip can well meet the need of the B-PLC system.

In complex environment, the wireline voltage driver should be compatible with wide terminal common-mode range, ESD and radiation interference. The most vulnerable devices in the conventional driver are the NMOS transistor and the SCR against negative ESD shock, total dose radiation and single event latch-up. In this paper, a reliable wireline driver circuit is proposed compatible with -7~12 V terminal common-mode voltage range. By adopting face-to-face diodes, PMOS/NPN hybrid driver and Schottky diodes, the proposed driver circuit demonstrates significant protection level improvement for both ESD and radiation. Both the reference SCR-based driver and the proposed driver with optimized circuit design and protection strategy are fabricated using a 0.6 μm BCD process. Due to simpler circuit structure, the proposed output stage has about 10% less chip area. According to the measurement results, HBM ESD level of 3 kV, total dose radiation level of 100 krad(Si), and single event effect level of 75 MeV·cm2/mg are achieved in the proposed design to satisfy complex environment applications.

This paper introduces a over-temperature protection (OTP) circuit used in line driver chip for PLC applications. For the limitations of the BJT process, the proposed circuit adopts a current distribution structure with a positive loop to realize state switching if the temperature exceeds the threshold or recovers, instead of the traditional structures with integrated comparators in the CMOS process. The method minimizes quiescent current (IQ) and transistor consumptions of the circuit. In addition, due to no comparator exists, there is no need for reference voltage, so that the process and voltage stabilities of the circuit are improved. The OTP circuit is implemented by SOI-BJT process, and relies on a line driver chip for verification. The module consumes 5-μA IQ, which only accounts for 0.02% of the whole chip. The measured maximum temperature drift of the circuit is 0.167 ∘C/V under the power supply voltage range of 6-30V, and the average hysteretic temperature drift of 6 random sampled chips is 0.15 ∘C.

A fully integrated low-power area-efficient receiver using a low–intermediate frequency topology for BDS-3 and GPS L1 bands is presented in this paper. Accurate localization can be achieved without requiring off-chip low-noise amplifiers. The receiver bandwidths for GPS and BDS-3 are 2 MHz and 4 MHz, respectively. Digitally assisted calibration schemes, such as RC calibration, automatic gain control, and DC offset correction are integrated to resist the effects of the process, voltage, and temperature (PVT) variations. The receiver—fabricated in a standard 55 nm CMOS technology—provides a maximum gain of 113.2 dB, a gain control range of 61 dB, and a minimum noise figure of 1.74 dB under a 1.2 V supply. The receiver, with and without the frequency synthesizer that provides the local oscillator frequency, consumes 8.7 mA and 4.8 mA, with areas of 0.73 mm² and 0.345 mm², respectively.