Physically Unclonable Functions (PUFs) are impacted by environmental variations and aging which can reduce their acceptance in identification and authentication applications. Prior approaches to improve PUF reliability include bit analysis across environmental conditions, better design, and post-processing error correction, but these are of high cost in terms of test time and design overheads, making them unsuitable for high volume production. In this paper, we aim to address this issue for SRAM PUFs with novel bit analysis and bit selection algorithms. Our analysis of real SRAM PUFs reveals (i) critical conditions on which to select stable SRAM cells for PUF at low-cost (ii) unexplored spatial correlation between stable bits, i.e., cells that are the most stable tend to be surrounded by stable cells determined during enrollment. We develop a bit selection procedure around these observations that produces very stable bits for the PUF generated ID/key. Experimental data from real SRAM PUFs show that our approaches can effectively reduce number of errors in PUF IDs/keys with fewer enrollment steps.

Counterfeit ICs can have a major impact on the security and reliability of critical applications. This paper presents a method called Secure Split-Test (SST) for securing the manufacturing process to prevent counterfeits, allowing intellectual property (IP) owners to protect and meter their IPs. This is done by requiring test results to be verified by the IP owner and by requiring the IP owner to provide a “key” to unlock the IPs correct functionality. The results and analysis demonstrate that SST can effectively prevent counterfeited ICs from untrusted foundries or assemblies as well as its resilience to attacks and circumvention.

Physical unclonable functions (PUFs) have emerged as a promising security primitive for low-cost authentication and cryptographic key generation. However, PUF stability with respect to temporal variations still limits its utility and widespread acceptance. Previous techniques in the literature have focused on improving PUF robustness against voltage and temperature variations, but the issues associated with aging have been largely neglected. In this paper, we address aging in the popular ring oscillator (RO)-PUF. We propose a new aging-resistant design that reduces sensitivity to negative-bias temperature instability and hot-carrier injection stresses. Simulation results demonstrate that our aging-resistant RO-PUF (ARO-PUF) can produce unique, random, and more reliable keys. On an average, only 3.8% bits of an ARO-PUF flip over a ten-year operational period because of aging, compared with a 12.8% bit flip for a conventional RO-PUF. The proposed ARO-PUF allows us to eliminate the need for error correction by adding extra ROs. The result shows that an ARO-PUF saves _~ 32x area overhead compared with a conventional RO-PUF with required error correction schemes for a reliable key.

Physical unclonable functions (PUFs) have emerged as a promising hardware security primitive, but existing CMOS PUFs suffer from issues related to reliability and susceptibility to modeling attacks. Memristors, leveraging nanotechnology fabrication process and highly nonlinear behavior, pose as an interesting alternative. In this paper, we report the first demonstration of memristor based PUFs. The six memristors we fabricated show a 50% uncertainty of PUF response and high reliability upon repeated interrogation. A physics based circuit model of memristors was also implemented to accurately determine the simulation time required for randomly selected polyominoes from a 3-D array of memristors. The proposed model provides higher degree of complexity and results in seven orders of increase in simulation time for an attacker than that reported by Rajendran , 2012.

The globalization of the semiconductor design and fabrication industry (also known as the horizontal business model) has led to many well-documented issues associated with untrusted foundries and assemblies, including IC overproduction, cloning, and the shipping of improperly or insufficiently tested chips. Besides the loss in profits to Intellectual Property (IP) owners, such chips entering the supply chain can have catastrophic consequences for critical applications. We propose a new Secure Split-Test (SST) scheme called the Connecticut SST (CSST) in which the IP owner takes full control over testing. In CSST, each chip and its scan chains are locked during testing, and only the IP owner can interpret the locked test results and unlock passing chips. The new SST can prevent overproduced, defective, and cloned chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry/assembly and the IP owner compared to the original version of the SST. The results demonstrate that our new technique is more secure than the original and has lower communication overheads.