Prof. Jung-Dong Park
Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea
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Academic Career Length
21Years (2006-Present)
(Calculated once Scilit publication data is synced: current year − year of first publication + 1)
Representative Publications
View All Publications15 December 2009 in IEEE Journal of Solid-State Circuits
Journal Article
CMCristian Marcu
Cristian Marcu
DCDebopriyo Chowdhury
Debopriyo Chowdhury
CTChintan Thakkar
Chintan Thakkar
Jung-Dong ParkLKLing-Kai Kong
Ling-Kai Kong
ANAli M. Niknejad
Ali M. Niknejad
+8
This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.
23 June 2015 in Nano Letters
Journal Article
JJJaesung Jo
Jaesung JoWCWoo Young Choi
Woo Young ChoiJung-Dong ParkJSJae Won Shim
Jae Won Shim
HYHyun-Yong Yu
Hyun-Yong Yu
CSChanghwan Shin
Changhwan Shin
26 September 2019 in IEEE Access
Journal Article
We present a wideband circularly polarized (CP) multiple-input multiple-output (MIMO) dielectric resonator antenna (DRA) with enhanced diversity. In the DRA element, two diagonal edges of the DR were truncated at 45° to obtain a wider axial ratio larger than 0.65 GHz. The DRA element was excited by a cross-ring slot with specific slot-arm ratio through microstrip-line (MSTL) implemented at the backside of the FR4 substrate to generate CP fields. Small triangular stands at the edge of the DR were employed to hold it in place to avoid any degradation from the uncontrollable bonding agent used for attaching DR onto the FR4 substrate. The DRA achieved an impedance bandwidth better than 0.8 GHz with an antenna gain of 4.83 dBi. Using the DRA with the MSTL feed, two-element CP-DRA array was implemented with electromagnetic band-gap (EBG) structure etched onto the ground plane of the MSTL. The proposed architecture achieves isolation better than 26 dB over the desired frequency band without any performance degradation while maintaining its compact size in the array. Various diversity analysis was carried out on the implemented circularly polarized MIMO DRA. The measured results demonstrated that the proposed singly fed DRA with EBG on the ground plate is suitable for implementing wideband circular polarized MIMO antennas in a compact size.
1 November 2016 in IEEE Transactions on Electron Devices
Journal Article
The effect of a triple metal-gate (TMG) on the performance and on the ambipolar current in a TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated using technology computer-aided design simulation. The TMG-TFET is designed to tackle the performance as well as the ambipolar current, simultaneously, by modulating the TMG parameters-the work function of the TMG and/or the length of each MG-that have critical impacts on the energyband diagrams of the channel region. The tempered on-/offcurrent ratio of 10 8 and the steep average subthreshold slope of 43.5 mV/decade at a power supply voltage of 0.5 V are ascribed to the formation of an energy barrier in the channel by the optimal device parameters. It is found that two main flaws in a conventional (single-material gate) TFET, which are the degraded on-state current and the ambipolar current, can be successfully controlled by adjusting the TMG structure.
31 August 2012 in IEEE Journal of Solid-State Circuits
Journal Article
A fully integrated transceiver operating at 0.38 terahertz (THz) has been demonstrated in 0.13 μm SiGe BiCMOS with fT = 230 GHz. We present a quadrature push-push harmonic circuitry consisting of the clamping pairs driven by balanced quadrature LO signals coupled through the transformers and the Coplanar Stripline (CPS). Harmonic generation of the clamping circuit is analyzed with a clamped sinusoidal model. Several terahertz circuits such as a quadrupler, a THz subharmonic mixer, and an IQ quadrature generator are implemented with the quadrature push-push circuitry to realize a homodyne FMCW radar. Radar functionality is demonstrated with ranging and detection of a target at 10 cm. The measured Equivalent Isotropically Radiated Power (EIRP) of the transmitter is -11 dBm at 0.38 THz and the receiver noise figure (NF) is between 35-38 dB while dissipating a power of 380 mW.
17 June 2019 in IEEE Access
Journal Article
About Me
Jung-Dong Park received a B.S. degree from Dongguk University, Seoul, Korea, in 1998; a M.S. degree from the Gwangju Institute of Science and Technology (GIST), Gwangju, Korea, in 2000; and a Ph.D. degree from the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley, in 2012.
From 2000 to 2002, he worked at the Institute for Advanced Engineering (IAE), Yongin, Korea, where he was involved with the design of 35-GHz radar/radiometer transceivers. From 2002 to 2007, he was a senior researcher at the Agency for Defense Development (ADD), Daejeon, Korea, where he was responsible for the development of millimeter-wave (mmW) passive/active sensors and related mmW modules. From 2007 to 2012, he was with the Berkeley Wireless Research Center (BWRC), where he worked on silicon-based RF/millimeter-wave/terahertz circuits and systems. From 2012 to 2015, he worked for Qualcomm Inc., San Jose, CA, USA, where he designed various RF/analog integrated circuits.
He is currently an Associate Professor at the Division of Electronics and Electrical Engineering, Dongguk University, Seoul. His research interests include wireless communications, remote sensors, microwave electronics, analog, RF, mixed-signal, and millimeter-wave circuits.
He was the recipient of the 2017 Most Frequently Cited Papers Award as a lead author from 2010 to 2016 at the 2017 IEEE Symposium on VLSI Circuits, Kyoto, Japan.