The Internet of Things (IoT) is defined as a paradigm in which objects equipped with sensors, actuators, and processors communicate with each other to serve a meaningful purpose. In this paper, we survey state-of-the-art methods, protocols, and applications in this new emerging area. This survey paper proposes a novel taxonomy for IoT technologies, highlights some of the most important technologies, and profiles some applications that have the potential to make a striking difference in human life, especially for the differently abled and the elderly. As compared to similar survey papers in the area, this paper is far more comprehensive in its coverage and exhaustively covers most major technologies spanning from sensors to applications.

Ensuring the functional correctness of Networks-on-Chip (NoC) can be particularly challenging, and communication-centric debug methodologies have been widely used by engineers to validate NoC functionality during post-silicon validation. Design-for-Debug structures such as trace buffers and monitors are usually inserted in such Systems-on-Chip to enhance signal visibility. However, this debug hardware becomes underutilized once the chip goes into production. While the size and organization of the router buffers directly impact network throughput, these buffers also dominate the on-chip router area. We propose a scheme AugVC to reuse trace buffers to augment router buffers, with the objective of improving the overall network performance. Experimental results for a 64-node mesh network show that our proposed approach can reduce latency by up to 38.25% for transpose traffic compared to a baseline design with reduced buffer sizes. We also propose an extension, Output Port directed Virtual Channel (ODVC), that uses a modified virtual channel assignment strategy, on the basis of the designated output port of a network packet. This strategy reduces the average packet latency and area of the router by 45% and 32.4%, respectively.

In this article, we propose a fast thermal modeling tool, 3DSim, using a Green's-function-based approach. Green's-function-based approaches have been shown to be faster than the traditional finite-difference-based techniques. Our proposed tool can model steady-state and transient thermal profiles for both 2-D and 3-D chips, which may contain multiple active layers and fluid-carrying microchannels for heat removal. The unique advantage of our tool is that it models leakage power analytically using a piecewise-linear leakage model, thereby eliminating the need to iterate multiple times through the leakage-temperature feedback loop. We use several algebraic techniques and transforms to compute the thermal profile analytically and thereby speedup the process of calculation. To the best of our knowledge, transform-based approaches have not been used before to model the temperature in 3-D chips with microchannels. Our approach provides a 150x speedup over state-of-the-art thermal simulators, with an error limited to 5%.

With the increasing complexity of modern systems-on-chip, the possibility of functional errors escaping design verification is growing. Postsilicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware, such as trace buffers, is inserted to aid postsilicon validation. In spite of its benefit, such hardware incurs area overheads that impose size limitations. However, the effective overhead could be reduced if the area dedicated to DFD could be reused in-field. In this paper, we present a novel method for reusing an existing trace buffer as a victim cache of a processor to enhance the performance. The trace buffer storage space is reused for the victim cache with a small additional controller logic. Simultaneous multithreading allows further fine-grained control of the victim cache, which can be shared between the threads based on the requirements of the applications. We also propose and evaluate different approaches to partition the victim cache between threads. Experimental results on several benchmark applications and trace buffer configurations show that the proposed approach can enhance the average performance by up to 8.3% with a minimal area overhead.