Noninvasive remote monitoring of hemodynamic variables is essential in optimizing treatment opportunities and predicting rehospitalization in patients with congestive heart failure. The objective of this study is to develop a wearable bioimpedance-based device, which can provide continuous measurement of cardiac output and stroke volume, as well as other physiological parameters for a greater prognosis and prevention of congestive heart failure. The bioimpedance system, which is based on a robust and cost-effective measuring principle, was implemented in a CMOS application specific integrated circuit, and operates as the analog front-end of the device, which has been provided with a radio-frequency section for wireless communication. The operating parameters of the proposed wearable device are remotely configured through a graphical user interface to measure the magnitude and the phase of complex impedances over a bandwidth of 1 kHz to 1 MHz. As a result of this study, a cardiac activity monitor was implemented, and its accuracy was evaluated in 33 patients with different heart diseases, ages, and genders. The proposed device was compared with a well-established technique such as Doppler echocardiography, and the results showed that the two instruments are clinically equivalent.

Wearable bioimpedance spectroscopy within Internet of Medical Things ecosystems requires energy-efficient analog front-ends (AFEs) capable of processing small impedance-dependent signals over a wide excitation-frequency range. This paper presents a preliminary study of an automated g_m/I_D-based framework for the co-design of wideband CMOS instrumentation amplifiers, jointly considering power, noise, bandwidth, and frequency-dependent common-mode rejection. The proposed flow combines technology-characterized device data, Verilog-A behavioral modeling, Python-based optimization, and SKILL-assisted transistor-level verification. The methodology is applied to a wideband CMOS current-feedback instrumentation amplifier (CFIA) designed in a 180-nm CMOS technology. Operating from a 1.8-V supply, the amplifier provides a nominal gain of 30 V/V over the 1-kHz to 2-MHz signal band. Particular attention is given to the coupling between transistor sizing, parasitic capacitance, and high-frequency CMRR in a local current-feedback topology. The paper establishes the BIS readout requirements, describes the selected CFIA architecture, and formulates the main design variables and optimization targets. The presented results constitute the initial stage of a broader design framework; complete optimization, statistical robustness, and experimental validation are reserved for the subsequent full study.