As one of the key techniques for resolution enhancement technologies (RETs), optical proximity correction (OPC) suffers from prohibitive computational costs as feature sizes continue to shrink. Inverse lithography techniques (ILTs) treat the mask optimization process as an inverse imaging problem, yielding high-quality curvilinear masks. However, ILT methods often fall short of printability and manufacturability due to their time-consuming procedures and excessive computational overhead. In this article, we propose DevelSet, a potent metal layer OPC engine that replaces discrete pixel-based masks with implicit level set-based representations. With a GPU-accelerated lithography simulator, DevelSet achieves end-to-end mask optimization using a neural network to provide quasi-optimized level set initialization and further evolution with a CUDA-based mask optimizer for fast convergence. The backbone of DevelSet-Net is a transformer-based multibranch neural network that offers a parameter selector to eliminate the need for manual parameter initialization. Experimental results demonstrate that the DevelSet framework outperforms state-of-the-art approaches in terms of printability while achieving fast runtime performance (around 1 s). We expect this enhanced level set technique, coupled with a CUDA/DNN accelerated joint optimization paradigm, to have a substantial impact on industrial mask optimization solutions.

Inverse lithography technique (ILT) is one of the most widely used resolution enhancement techniques (RETs) to compensate for the diffraction effect in the lithography process. However, ILT suffers from runtime overhead issues with the shrinking size of technology nodes. In this article, our proposed L2O-ILT framework unrolls the iterative ILT optimization algorithm into a learnable neural network with high interpretability, which can generate a high-quality initial mask for fast refinement. Experimental results demonstrate that our method achieves better performance on both mask printability and runtime than the previous methods.

Source mask optimization (SMO) is vital for mitigating lithography imaging distortions caused by shrinking critical dimensions in integrated circuit fabrication. However, the computational intensity of SMO, involving multiple integrals in Abbe’s theory, hinders its widespread adoption and advancement. In this article, we present Diff-SMO, a highly efficient and accurate SMO framework with a primary emphasis on enhancing source optimization techniques. Previous research was confined to mask optimization acceleration due to the constraints of the academia lithography model. Diff-SMO extends the scope of optimization by concurrently refining the intricate interplay between the source and mask. We first develop a GPU-accelerated lithography simulator grounded in Abbe’s theory, enabling full GPU acceleration throughout the SMO process. Furthermore, we propose a discrete diffusion model for generating quasi-optimal sources, significantly improving computational efficiency. Our experimental results demonstrate exceptional imaging fidelity, surpassing the state-of-the-art, with over 200 times higher throughput compared to traditional SMO methods.

Despite recent advances, analog front-end design still relies heavily on expert intuition and iterative simulations, which limits the potential for automation. We present AnalogCoder-Pro, a multimodal large language model (LLM) framework that unifies the stages of circuit topology generation and device sizing optimization. The framework features a multimodal diagnosis-and-repair feedback loop that uses simulation error messages and waveform images to autonomously correct design errors. It also builds a reusable circuit tool library by archiving successful designs as modular subcircuits, accelerating the development of complex systems. Furthermore, it enables end-to-end automation by generating circuit topologies from target specifications, extracting key parameters, and applying Bayesian optimization for device sizing. On a curated benchmark suite covering 13 circuit types, AnalogCoder-Pro successfully designed 28 circuits and consistently outperformed existing LLM-based methods in figures of merit.

Analog routing is crucial for performance optimization in analog circuit design, but conventionally takes significant development time and requires design expertise. Recent research has attempted to use machine learning (ML) to generate guidance to preserve circuit performance after analog routing. These methods face challenges such as expensive data acquisition and biased guidance. This article presents AnalogFold, a new paradigm of analog routing that leverages ML to provide performance-oriented routing guidance. Our approach learns performance-driven routing guidance and uses it to help automatic routers for performance-driven routing optimization. We propose to use a 3DGNN that incorporates cost-aware distance to make accurate predictions on post-layout performance. A pool-assisted potential relaxation process derives the effective routing guidance. The experimental results on multiple benchmarks under the TSMC 40 nm technology node demonstrate the superiority of the proposed framework compared to the cutting-edge works.