Memristor-based design has gained significant attention in recent years due to its potential to revolutionize various fields such as artificial intelligence, neuromorphic computing, non-volatile memory, signal processing, filtering, and radio frequency design. These emerging devices offer unique advantages such as non-volatile memory, low power consumption, and a high integration density. Their scalability and compatibility with existing fabrication processes make them an attractive option for industry adoption, paving the way for faster and more efficient architecture design. Researchers are actively exploring ways to optimize memristor technology for practical applications to harness its full potential. This includes developing novel materials and structures as well as improving the reliability and performance of memristors in various applications. This paper provides a comprehensive overview of the current advancements in memristor technology and their potential impact on the design of future electronic systems, focusing on its applications in the analog domain. By exploring the latest research and development in this field, researchers can gain valuable insights into how analog memristors can be integrated into their designs to achieve enhanced performance and efficiency. The paper delves into the fundamental principles of memristor technology, exploring its unique characteristics and advantages over traditional electronic components. It discusses the potential impact of memristors and challenges in the analog field of electronics, and highlights the progress made in their integration with existing circuitry, enabling novel functionalities and improved performance. Furthermore, it highlights ongoing research efforts to improve the performance and reliability of memristors, as well as the potential limitations and challenges that need to be addressed for widespread adoption, including variability in performance and reliability.

Memristors, as the fourth fundamental circuit element, have attracted significant interest for their potential in analog signal processing, computing, and memory storage technologies. However, physical memristor implementations still face challenges in reproducibility, scalability, and integration with standard CMOS processes. Memristor emulator circuits, implemented using analog, digital, and mixed components, have emerged as practical alternatives, offering tunability, cost effectiveness, and compatibility with existing fabrication technologies for research and prototyping. This review paper provides a comprehensive analysis of recent advancements in memristor emulator design methodologies, including active and passive analog circuits, digital implementations, and hybrid approaches. A critical evaluation of these emulation techniques is conducted based on several performance metrics, including maximum operational frequency range, power consumption, and circuit topology. Additional parameters are also taken into account to ensure a comprehensive assessment. Furthermore, the paper examines promising healthcare applications of memristor and memristor emulators, focusing on their integration into biomedical systems. Finally, key challenges and promising directions for future research in memristor emulator development are outlined. Overall, the research presented highlights the promising future of memristor emulator technology in bridging the gap between theoretical memristor models and practical circuit implementations.

The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme’s low area burden, high efficiency and working frequency.

This paper presents a novel passive floating memristor emulator that operates without an external DC bias, leveraging the DTMOS technique. The design comprises only four MOSFETs and eliminates the need for external capacitors. The emulator achieves a high operating frequency of around 250 MHz and consumes zero static power. A comprehensive analysis and simulation, conducted using 180 nm CMOS technology, validates the circuit’s performance. The versatility and effectiveness of the proposed emulator are demonstrated through its application in various circuits, including logic gates, a ring oscillator, and analog filters, highlighting its potential for diverse low-power, high-frequency applications. The proposed emulator provides a compact, efficient, and integrable solution for nanoelectronic circuit designs.

This study presents transistor-level simulation results for a novel memristor emulator circuit. The design incorporates an inverter and a current-mode-controlled operational transconductance amplifier to stabilize the output voltage. Transient performance is evaluated across a 20 MHz to 100 MHz frequency range. Simulations using 0.18 μm TSMC technology confirm the circuit’s functionality, demonstrating a power consumption of 0.1 mW at a 1.2 V supply. The memristor model’s reliability is verified through corner simulations, along with Monte Carlo and temperature variation tests. Furthermore, the emulator is applied in a Memristive Integrate-and-Fire neuron circuit, a CMOS-based system that replicates biological neuron behavior for spike generation, enabling ultra-low-power computing and advanced processing in retinal prosthesis applications.

Cryptographic devices’ complexity necessitates fast security simulation environments against fault attacks. SystemC, a promising candidate in Electronic System Levels (ESLs), can achieve higher simulation speeds while maintaining accuracy and reliability, and its modular and hierarchical design allows for efficient modeling of complex cryptographic algorithms and protocols. However, code modification is required for fault injection and detection. Aspect-Oriented Programming (AOP) can test cryptographic models’ robustness without modifications, potentially replacing real cryptanalysis schemes and reducing the time and effort required for fault injection and detection. Through the utilization of a fault injection/detection environment, this paper presents a novel approach to simulating the security fault attacks of ASCON cryptographic systems at the ESL. The purpose of this methodology is to evaluate the resistance of ASCON SystemC models against fault attacks. The proposed methodology leverages the advantages of AOP to enhance the fault injection and detection process. By applying AOP techniques, we inject faults into the SystemC models without making any changes to the main codebase. This approach not only improves the efficiency of testing cryptographic systems but also ensures that the main functionality remains intact during the fault injection process. The methodology was validated using three scenarios and SystemC ASCON as a case study. The first simulation involved evaluating fault detection capabilities, the second focused on the impact of AOP on executable file size and simulation time, and the third focused on the ESL impact on the ASCON design process. Simulation results show that this methodology can perfectly evaluate the robustness of the ASCON design against fault injection attacks with no significant impact on simulation time and file executable size. Additionally, the simulation results prove that the ASCON development life cycle at the ESL reduces the amount of time devoted to the design procedure by 83.34%, and the ASCON security attack simulations at the ESL decrease the simulation time by 40% compared to the register transfer level (RTL).