One of the key metrics used for defying the security of the Internet of Things (IoT) is data integrity, which mostly relies on the use of cryptographic hash functions. In the last years, the National Institute of Standards and Technology (NIST) announced SHA-3 as the new standard for better security. SHA-3 is also exploited in most of the current post-quantum cryptographic (PQC) protocols. Nevertheless, the used algorithm, i.e. Keccak, is computationally heavy and consequently limits its utilization in RISC-V-based Systems on Chip (SoC). In this work, a Keccak accelerator is proposed to speed up SHA3 computations for the CRYSTALS-Kyber algorithm on the RISCV-based advanced microcontroller PULPissimo. Compared to the plain SW implementation on RISC-V, our results show a speedup factor of up to 2.79 at the expense of a 12.4% resources overhead.

Once powerful enough quantum computers become feasible, many of the regularly used cryptosystems will be completely useless. Thus, designing quantum-safe cryptosystems to replace current algorithms is more crucial than ever. This paper presents the hardware implementation of one of the fundamental building blocks of all post-quantum cryptographic (PQC) algorithms, which are PQC-primitives, having NIST-PQC-finalists CRYSTALS-Kyber algorithm as a target. This work analyzes Keccak sponge function and the four SHA-3 algorithms used in CRYSTALS-Kyber, realizing the correct processing and handling of input information and integrating the four standards into one implementation for Kyber-III level of security. The synthesis results are provided for 65-nm technology, while Artix7 XC7A75-3 is chosen as the implementation platform. The efficiency and the performance of the proposed architecture are compared in terms of area, frequency, clock cycles, and efficiency with the state-of-the-art.

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors.

Any cryptographic system strongly relies on randomness to ensure robust encryption and masking methods. True Random Number Generators play a fundamental role in this context. The National Institute of Standards and Technology (NIST) and the Bundesamt für Sicherheit in der Informationstechnik (BSI) provide guidelines for designing reliable entropy sources to fuel cryptographic Random Bit Generators. This work presents a highly parameterized, open-source implementation of a TRNG based on ring oscillators, complemented by an optimized Keccak conditioning unit. The design process is accompanied by a thorough study of the relevant literature and standards, specifying the requirements for reliable entropy sources in cryptographic systems. The design of the TRNG proposed in this paper aims to strike a balance between area, throughput, power consumption, and entropy, while adhering to these guidelines. The proposed design has undergone extensive testing and validation and has successfully passed the NIST SP 800-22, NIST SP 800-90B, and BSI AIS-31 tests, achieving a min-entropy per bit of 0.9982 (NIST) and 0.9998 (BSI).

ATHOS (Accelerated Technology for Hardware Optimization with RISC-V) is introduced as a robust solution for enhancing cryptographic operations, explicitly designed for RISC-V architectures. Addressing the challenges of implementing cryptographic algorithms, ATHOS leverages a combination of both tightly and loosely coupled accelerators. A key innovation of ATHOS is its exploitation of the CV32E40X core via the novel Core-V eXtension InterFace (CV-X-IF). This pioneering work is one of the first to utilize this interface in real-world applications, offering a unique foundation for extensive exploration of acceleration approaches. Utilizing the CV-X-IF simplifies the insertion of new instructions into the Instruction Set Architecture (ISA) and streamlines the integration of tightly coupled accelerators without requiring modifications to the toolchain. This work focuses on the implementation and integration of various accelerators into the RISC-V microcontroller X-HEEP, adding new instructions and external IPs for the Numeric Theoretic Transform (NTT), its Inverse (INTT), and Keccak transformation. Our complete architecture is implemented on ASIC 65μm technology, resulting in a 1.47× area overhead for the microcontroller. Additionally, it improves CRYSTALS-Kyber’s and CRYSTALS-Dilithium’s total clock cycle respectively by up to 7.74× and to 4.12× compared to the baseline software implementation, demonstrating the potential of this hybrid system and marking one of the first real applications of the CV-X-IF interface.

This paper presents a comprehensive study on the implementation of a RISC-V-based memory-mapped accelerator designed for Number Theoretic Transform (NTT) and Inverse Number Theoretic Transform (INTT) operations within the context of the post-quantum cryptographic algorithm CRYSTALS-Kyber. The primary focus lies in the performance evaluation of the algorithm, with a particular emphasis on minimizing the overhead associated with transferring data between the core and the implemented IP. The analysis includes a deep dive into the intricacies of data transfer, leveraging Direct Memory Access (DMA) to efficiently reduce overhead. The evaluation results show that our approach, when applied to a X-HEEP core, achieves up to 15.7× and 19.6× improvement in cycle count for NTT and INTT respectively, compared to the base software implementation. To this end, we also demonstrate the efficacy of the proposed memory-mapped accelerator in enhancing the overall performance of CRYSTALS-Kyber, thereby contributing to the advancement of secure cryptographic systems in the post-quantum era.