Moore's law is approaching its physical limit. Tunneling field-effect transistors (TFETs) based on 2D materials provide a possible scheme to extend Moore's lawdown to the sub-10-nm region owing to the electrostatic integrity and absenceof dangling bonds in 2D materials. We report an ab initio quantum transport study on the device performance of monolayer (ML) black phosphorene (BP)TFETs in the sub-10-nm scale (6–10 nm). Under the optimal schemes, the ML BP TFETs show excellent device performance along the armchair transport direction.The on-state current, delay time, and power dissipation of the optimalsub-10-nm ML BP TFETs significantly surpass the latest International TechnologyRoadmap for Semiconductors (ITRS) requirements for high-performance devices. The subthreshold swings are 56–100 mV/dec, which are much lower than those of their Schottky barrier and metal oxide semiconductor field-effect transistor counterparts. Open image in new window

The development of air-stable channels with a high on-state current (I_on) is in high demand for the feasible application of TFETs. Monolayer group IV mono-chalcogenides (i.e., GeS, GeSe, SnS, and SnSe), as emerging air-stable atomic-thin semiconductors, are potential channels for sub-10 nm tunneling field-effect transistors due to their high carrier mobility and anisotropic electronic properties. Herein, we investigated the performances of sub-10 nm monolayer (ML) group IV mono-chalcogenide TFETs using ab initio quantum transport simulation. The ML GeSe TFET exhibited the best performance with regards to both high I_on and low leakage current (I_leak) among the four devices, followed by the ML SnSe TFET with a high I_on. The I_on of the optimal ML GeSe TFET with a physical gate length of L_g = 10 nm surpasses the International Technology Roadmap for Semiconductors (ITRS, 2013 Edition) requirements for high-performance (HP) and low-power (LP) devices, simultaneously, and that of the ML SnSe TFET with L_g = 10 nm surpasses the requirement of ITRS HP devices. In combination with our former works, we suggest an E_g of 0.77–1.19 eV and of 0.11–0.15m₀ to search for competitive 2D channels with a high I_on for HP application in TFET devices with a planar homogeneous p–i–n architecture.

Monolayer hexagonal arsenene, antimonene, and bismuthene are emerging two-dimensional (2D) semiconductors. We explore the possibility of their applications on 10 nm gate long tunneling field effect transistors (TFETs) from the ab initio quantum transport simulation. We predict that the ML bismuthene TFET has the largest on-state current I _on (1153 μ A μ m ⁻¹ ) among the three checked hexagonal group V-enes ones for high-performance (HP) application. We further propose a prototype negative capacitance TFET, where a ferroelectric dielectric is adopted in the TFET to improve the device performance. The resulting I _on is dramatically elevated to 1868 μ A μ m ⁻¹ , which has met the requirement of International Technology Roadmap for Semiconductors for HP devices (1450 μ A μ m ⁻¹ ). Therefore, the combination of 2D semiconductor channel and negative capacitance technique breaks the bottleneck of a very low on-state current of conventional TFETs.

Two-dimensional (2D) semiconductors are attractive channels to shrink the scale of field-effect transistors (FETs), and among which the anisotropic one is more advantageous for a higher on-state current (I_on). Monolayer (ML) SnSe₂, as an abundant, economic, nontoxic, and stable two-dimensional material, possesses an anisotropic electronic nature. Herein, we study the device performances of the ML SnSe₂ metal-oxide-semiconductor FETs (MOSFETs) and deduce their performance limit to an ultrashort gate length (L_g) and ultralow supply voltage (V_dd) by using the ab initio quantum transport simulation. An ultrahigh I_on of 5,660 and 3,145 µA/µm is acquired for the n-type 10-nm-L_g ML SnSe₂ MOSFET at V_dd = 0.7 V for high-performance (HP) and low-power (LP) applications, respectively. Specifically, until L_g scales down to 2 and 3 nm, the MOSFETs (at V_dd = 0.65 V) surpass I_on, intrinsic delay time (τ), and power-delay product (PDP) of the International Roadmap for Device and Systems (IRDS, 2020 version) for HP and LP devices for the year 2028. Moreover, the 5-nm-L_g ML SnSe₂ MOSFET (at V_dd = 0.4 V) fulfills the IRDS HP device and the 7-nm-L_g MOSFET (at V_dd = 0.55 V) fulfills the IRDS LP device for the year 2034.

The successful fabrication of sub-5 nm 2D MoS ₂ field-effect transistors (FETs) announces the approaching post-silicon era. It is possible for tunneling field-effect transistors (TFETs) based on monolayer black phosphorene (ML BP) to work well in the sub-5 nm region because of its moderate direct band gap, anisotropic electronic properties and high carrier mobility. We simulate the device performance limit of the ML BP TFETs at the sub-5 nm scale using ab initio quantum transport calculations. We predict that the on-state currents ( I _on ) of the sub-5 nm ML BP TFETs will exceed those of the ML WTe ₂ TFETs, which possess the highest I _on among the transition-metal dichalcogenide family. In particular, the I _on of the ML BP TFETs can fulfill the 2028 requirements of the international technology roadmap for semiconductors (ITRS) for the high-performance (HP) devices until the gate length is scaled down to 4 nm, while the delay times and power dissipations always surpass the 2028 requirements of the ITRS HP devices significantly in the whole sub-5 nm region.