Time-to-digital converter designing and analysis for asynchronous ADCs is discussed in the paper. The proposed ADC utilizes two-level conversion scheme consisting in duty-cycle modulation and subsequent time-to-digital conversion (TDC). Three concepts of the asynchronous ADC digital serial output interface are presented. The comparison of minimum transmission rates of the serial output port(s) for each concept is carried out. Finally, the procedure of the evaluation of key ADC design parameters for the speech signal supporting a possible original input signal recovery is exemplified.

The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.

The paper is focused on a development of a feedback-based architecture for successive-approximation time-to-digital converter (SA-TDC). The adoption of the feedback-based rather than feedforward architecture for the n-bit SA-TDCs is inspired by the classic successive approximation voltage-to-digital converter and motivated by a possible reduction of the number of time comparators from n to one. Nevertheless, existing developments of the feedback-based SA-TDC are characterized by much longer conversion time than that for feedforward SA-TDCs. In the paper, a concept of the feedback-based SA-TDC with dynamic equalization of logic propagation delays in the feedback loops is presented. The use of this technique allows to maintain the conversion time of the feedback-based SA-TDC the same as for the feedforward SA-TDC with just a single time comparator.

The new IEEE 802.11 standard version, denoted by 802.11e, was developed in order to introduce mechanisms enabling handling of real time applications. In order to achieve the goal, the transmission channel access control procedure was modified. The new approach consists in distinguishing the time after which packet transmission of a certain class may begin. The developed mechanism is not yet deterministic, but based on the principle of increasing the probability of success. In consequence, quality of service levels (QoS) guaranteed by the network to different applications may be strongly dependent not only on the type and intensity of input traffic, but also on up-to-date results of random processes realised in different stations. The first part of this paper contains short descriptions of the original and modified method of controlling access to the transmission channel. Using the further presented results of simulation tests it is possible to determine system operation intervals in which the network guarantees the required quality of service to traffic streams of a given class. The summary contains most important conclusions from the comparison of working principles of both mechanisms as well as the executed experiments