Jose Antonio Juárez-abad

Dr. Jose Antonio Juárez-abad

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Research Focus & Metrics

Academic Career Length

14Years (2013-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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23 November 2021 in IEEE Transactions on Industry Applications
Verified
Journal Article
Closed access
JLJesús Linares-Flores
Jesús Linares-Flores
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
AHArturo Hernandez-Mendez
Arturo Hernandez-Mendez
OCOmar Castro-Heredia
Omar Castro-Heredia
José Fermi Guerrero CastellanosJosé Fermi Guerrero Castellanos
José Fermi Guerrero Castellanos
GCG. Curiel-Olivares
G. Curiel-Olivares
This article presents a new control strategy merging a Sliding Mode Control (SMC) with a linear extended state observer (LESO) to regulate the output voltage of the buck-boost power converter system affected by matched and mismatched disturbances. The SMC-LESO schema uses the input-output linearization approach and the equivalent control method to determine the boundary layer around the sliding surface. This boundary layer depends on the sliding surface and the equivalent control value, depending on the estimated variables obtained through a LESO. With this schema, the unknown matched, and mismatched disturbances are observed and compensated by an adaptation of the SMC. The proposed approach minimizes the sliding surface chattering and improves the performance against sudden static and dynamic load changes as well as \textcolor{blue}{voltage variations on power supply input}. An experimental comparison with traditional sliding mode control (TSMC) and classical PID control is performed, confirming the proposal's effectiveness. The closed-loop stability (observer-controller-plant) guarantees in the Input-to-State Stability (ISS) framework.

23 January 2013 in IEEE Transactions on Industrial Informatics
Verified
Journal Article
Closed access
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
JLJesús Linares-Flores
Jesús Linares-Flores
EGEnrique Guzman-Ramirez
Enrique Guzman-Ramirez
HSHebertt Sira-Ramirez
Hebertt Sira-Ramirez
This paper presents a robust linear generalized proportional integral (GPI) control scheme for the output reference trajectory tracking task on a multilevel single-phase “buck” inverter. The scheme is shown to be robust with respect to arbitrary time-varying load current demands, acting as perturbation inputs to the inverter, and to significant converter parameter variations. The discrete time version of the control scheme is implemented on a field-programmable gate array hardware. Several laboratory robustness tests are performed on the controlled inverter with excellent results.

14 August 2018 in IEEE Transactions on Industrial Informatics
Verified
Journal Article
Closed access
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
ASArturo Pablo Sandoval-Garcia
Arturo Pablo Sandoval-Garcia
JLJesús Linares-Flores
Jesús Linares-Flores
José Fermi Guerrero CastellanosJosé Fermi Guerrero Castellanos
José Fermi Guerrero Castellanos
PSPedro Bañuelos Sanchez
Pedro Bañuelos Sanchez
MCMarco Antonio Contreras-Ordaz
Marco Antonio Contreras-Ordaz
This paper presents the design and embedded implementation of a robust controller for the transformerless multilevel active monophase rectifier. In order to reduce the effects caused by the uncertainty originated by the output load, an algebraic estimator is devised. Then, a linear controller based on the Exact Static Error Dynamics Passive Output Feedback (ESEDPOF) is proposed, where the uncertainty estimation is taken into account. Since the controller estimator is based on the continuous time plant model, its real-time implementation in a digital platform requires a discretization of the controller under sufficiently fast sampling, such that the properties of the closed loop nonlinear sampled data system are preserved. For this reason, the medium-scale FPGA Spartan-6 XC6SLX16 is used for implementing the ESEDPOF controller, the online algebraic estimator, the enhanced phase locked loop (EPLL), and the multilevel PWM. The parallel processing provided by these devices and the capability in the design of custom modules, allow optimizing the hardware description and obtaining an update time for the control law of 9.683 micro seconds. Experimental validation shows an excellent dynamical performance and a nearunit power factor.

1 June 2016
Verified
Conference Paper
Closed access
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
JLJesús Linares-Flores
Jesús Linares-Flores
MCM. A. Contreras-Ordaz
M. A. Contreras-Ordaz
This paper deals with the design and development of conventional Level-shifted PWM techniques in a field programmable gate array (FPGA) for asymmetrical converters in a Trinary Hybrid Multilevel Inverter topology. Each modulation technique has been implemented in FPGA through a 32-bit single precision floating point architecture in accordance to IEEE-754 standard. Portability to other devices is ensured using VHDL. Embedded Block RAMs minimize FPGA resource usage, saving general logic resources, increasing overall speed and reducing power consumption. A comparison is presented in terms of resource consumption. An Asymmetric Cascaded Multilevel Inverter of single-phase nine-level is developed using Nexys 2 FPGA Card Board with Spartan-3E 1200. Experimental results are based on a two H-Bridged hardware prototype.

17 December 2021 in Revista Iberoamericana de Automática e Informática Industrial
Verified
Journal Article
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JBJorge Luis Barahona-Avalos
Jorge Luis Barahona-Avalos
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
GGG. S. Galván-Cruz
G. S. Galván-Cruz
JLJesús Linares-Flores
Jesús Linares-Flores
Este artículo presenta una aproximación mediante rechazo activo de perturbaciones para controlar, de manera indirecta, la temperatura de la cara fría de un módulo termoeléctrico alimentado por un convertidor CD-CD tipo reductor. La dinámica del módulo, es vista como una perturbación de naturaleza desconocida y variante en el tiempo, del voltaje de salida del convertidor. Dicha perturbación es estimada mediante un observador de tipo proporcional integral generalizado, el cual en combinación con el controlador permite regular la temperatura en la cara fría del módulo termoeléctrico a un valor constante deseado. El observador diseñado estima de manera simultánea el voltaje de salida del convertidor reductor y la perturbación exógena en un esquema de cancelación en línea, conocido como control mediante rechazo activo de perturbaciones. Para propósitos de comparación, se diseñan un controlador de tipo proporcional integral y un regulador cuadrático lineal, sobre la base de una linealización aproximada del modelo dinámico combinado del convertidor reductor y del módulo. Los resultados experimentales que se obtuvieron mediante un prototipo experimental, permiten mostrar la efectividad de la técnica de control propuesta para este tipo de dispositivos termoeléctricos.

25 November 2023 in Fractal and Fractional
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Journal Article
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JMJuan Javier Montesinos-García
Juan Javier Montesinos-García
JBJorge Luis Barahona-Avalos
Jorge Luis Barahona-Avalos
JLJesús Linares-Flores
Jesús Linares-Flores
JJJose Antonio Juárez-abad
Jose Antonio Juárez-abad
This paper presents a novel control strategy based on an uncertainty estimator for a class of fractional-order nonlinear systems characterized by a polynomial input. The proposed strategy allows the system to be controlled without resorting to transformations or approximate linearization. This is accomplished by using a fractional-order sliding-mode observer, whose task is to estimate certain portions of the state of the nonlinear system of a non-integer order, thus allowing the control law to counteract these elements to steer the system towards a desired behavior. To validate the performance of the proposed strategy, it was implemented, both in simulation and experimentally, to regulate the temperature of the cold side of a thermoelectric module fed by a DC/DC electronic power converter of the step-down type, a system that is known to have a nonlinear polynomial-type control input.