This paper describes a digital-mapping direct digital frequency synthesizer having a tuning and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic microwave-integrated circuit (MMIC) is the first solution supporting a sampling rate of 7 GS/s with frequency modulation, phase modulation (PM), and amplitude modulation (AM) in the digital domain. It includes a 14 bits pipelined ripple-carry phase adder and a 10-bits high-speed amplitude multiplier. The minimum frequency, phase, and amplitude steps are 417.2 Hz, 0.022°, and 1.17 mV, respectively. A proof-of-concept chip with an active area of 0.23 mm2 was fabricated in a 1P9M 65-nm CMOS process and characterized in low-profile quad flat package (LQFP). The worst case wideband/narrowband spurious-free dynamic range is 32/42 dBc. This system consumes 85.9 mW/(GS/s) from a 1.2-V power supply when the PM/AM are enabled, resulting in an figure of merit (FoM) of 469.6 GS/s · 2(SFDR/6)/W. The absolute single sideband phase noise at 100 KHz offset from the carrier was better than -125 dBc/Hz in all the evaluated frequencies. A latency of 12.86 ns was measured when operating at 7 GS/s.

A 7GS/s DDFS MMIC featuring a Two-Times Interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for Random Swapping Thermometer Coding Dynamic Element Matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s-2^(SFDR/6)/W. A Proof-of-Concept chip with an active area of only 0.22mm² was measured in LQFP packages.

This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations respectively. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 85.9mW/(GS/s) from a 1.2V power supply when the amplitude/phase modulations are enabled, resulting in a FoM of 469.6GS/s-2^(SFDR/6)/W. A proof-of-concept chip with an active area of 0.23mm² was characterized in LQFP packages.

Worldwide, the technological change of Analog Television into Terrestrial Digital Television started since 1998. It's an inevitable change that each country has to face and which is part of the digitizing process that already has taken place in many other technologies. In order to determine the most convenient standard for Cuba, and technological infrastructure planning, it was necessary to take into account several aspects, particular technological issues. This paper comprises the evaluation of reception quality parameters for DTMB digital television signal broadcasting standard, with 6MHz bandwidth. DTMB has been adopted after more than ten years of work conducted by a Technical Committee created with this purpose. All the experiments have been carried out according to the UIT-R BT.2035-2 report: “Guidelines and techniques for the evaluation of digital terrestrial television broadcasting systems including assessment of their coverage areas”. The objective of Digital Terrestrial Television Broadcasting (DTTB) testing and trials is to evaluate the performance of an available system in a variety of transmission configurations and reception conditions. These tests include measurements of receiver performance in the presence of Random Noise, RF signal level Variation (Dynamic Range) and Static Multipath Interference.