Protective relays play a fundamental role in power systems, whose functions consist of three parts, namely protection, automation, and control, thus called the PAC altogether. It turns out that the architecture of a PACS (protection, automation, and control system) may exert a direct impact on the reliability of protective relay systems, previous studies of which are often conducted on the assumption that intelligent electronic devices (IEDs) have a constant fault rate with only mission reliability of the systems considered. To obtain a more accurate evaluation of system reliability bearing system maintenance in mind, this article proposes a novel method to appraise the reliability of PACSs with integrated consideration of basic and mission reliability. Firstly, the basic reliability of IEDs is calculated by parts count prediction, which will provide a more precise fault rate of IEDs. Secondly, the reliability of PACSs is analyzed by the reliability diagram and Markov model. By using the parts count prediction method to calculate the failure rate of the device, the steady-state probability rate will be accurate more than 0.0107%. At last, a quantitative criterion is finalized for selecting a suitable architecture easily.

IEC 61850 is the first and only global standard for substation automation. It standardizes all the communication interfaces, data module and information in the substation. There are three functional levels in substation: station, bay, and process. The sampled values (SV) data and Generic object oriented substation event (GOOSE) messages are transmitted through Ethernet in process bus. In peer-to-peer Ethernet communication mode, the digital relays are connected to lots of merging units (MU) directly to receive SV data and exchange GOOSE message with other intelligent electronic devices (IEDs). This requires so many Ethernet ports that no applicable processor can provide. Because the SV data and GOOSE message are time critical information, they should be transmitted and received as quickly as possible; the process time of SV data and GOOSE message may affect the digital relays' performance greatly. A multi-port Ethernet interface preprocessor board is developed to solve the above problems. The preprocessor board can provide enough Ethernet ports to meet the Ethernet port requirement. The hardware architecture of the preprocessor board is given, field programmable gate array (FPGA) functions, system update scheme and application scheme are explained in detail. At last, a real application of the preprocess board is given.

The digital sampling function is an important IP (Intelligent Property) in the power system specific processor. In the process of processor chip design verification, the verification of this IP cannot be completed due to the low frequency of the FPGA emulated processor. This paper proposes a method of slow release of sampled values. By delaying the release of the received SV (Sampled Value) data to the analog calculation task, the verification of digital sampling IP is implemented without modifying the protection algorithm program. And the tester is a universal digital relay protection tester. This method can be used not only for the verification of digital sampling IP, but also for the verification of analog sampling control IP, which speeds up the verification process of the processor chip and improves the coverage of verification.

This paper introduces the verification method of power system application specific processor and the power system application specific function modules in the processor. The verification is done from the application view in designing the power system specific processor. By tracing the signal stream and the data stream, the signal data path method is used to segregate the problem by segmentation. The function verification of the processor is done by using test equipment such as an oscilloscope and a function generator commonly used in the laboratory. In the case that the processor, the power specific function module and the operating system may need to be modified, the method is used to shorten the verification process of the processor. And the method also simplifies the verification. For the performance of the FPGA emulation processor is very low, the frequency-down method is introduced to verify the application functions. These two methods speed up the whole verification of the processor.