Dual active bridge (DAB) converter is one of the most popular bidirectional isolated dc/dc converters. Comparing with the two-level DAB converter, the multilevel DAB topologies take advantages of providing more control degrees of freedom to enhance the control flexibility. Therefore, these topologies are promising alternatives for wide voltage range applications. This article proposed an optimizing modulation strategy for neutral-point-clamped hybrid three-level dual active bridge (NH3L-DAB) converter to minimize the rms value of inductor current and the conduction losses. First, the basic operating principle of NH3L-DAB is analyzed comprehensively in the article. Afterward, the concept of global optimal condition is employed to derive the optimal modulation, and the corresponding analytical expressions of the control coordinates for rms current minimization are derived. By applying the optimal modulation strategy, NH3L-DAB facilitates to break the performance barriers of the prior-of-art of two-level DAB converter when the voltage transmission ratio has large variation. Finally, a bidirectional prototype with 200–450 V input and 20–28.8 V output is built to demonstrate the superior performance of the proposed optimal modulation strategy, and the detailed explanation of the experimental results is given as well.

Due to the quick development of wide bandgap power devices, the power density of the converters is expected to be much higher. In order to increase the power density and efficiency of the DAB converter, especially the efficiency under light load, a quasi-optimal current root-mean-square (RMS) control strategy to achieve All-ZVS is proposed by taking the inductor RMS current optimization algorithm into account in this paper. First the constraint conditions for realizing ZVS of all switching devices under different operating modes are concluded by analyzing the switching mode and the working principle of the DAB converter under the triple phase shift (TPS) modulation. The ZVS domain for All-ZVS operation in each operating mode is further obtained. Then, the GOC strategy is combined with the ZVS condition to derive the novel modulation for all operating modes. Based on this scheme, the switching conditions of all switches can be improved, and the efficiency of the DAB system under the light load is optimized. With ZVS operation, the switching frequency can be raised. Finally, a GaN HEMT based prototype of DAB converter was built and the switching frequency is 200kHz, the effectiveness of the proposed modulation scheme was verified by the experimental results.

Fault ride-through (FRT) control and protection are of vital importance for a modular multilevel converter-based high-voltage direct current (MMC-HVDC) system when dc-side pole-to-pole (PTP) or pole-to-ground (PTG) fault occurs. In this paper, a FRT strategy by reversing dc voltage polarity is proposed for symmetrical bipolar full-bridge submodule-based MMC-HVDC system. It is suitable for both PTP and PTG faults. By adopting this method, the dc voltage stress in PTG fault scenario and dc current stress in PTP fault scenario are eliminated. Meanwhile, the capability of transmitting rated active power is maintained during faults, which can minimize the impact of dc-side faults on ac grid. In addition, based on a deduced dc-side equivalent circuit, the dc line current oscillation phenomenon during FRT transient process is analyzed. An active damping control method is presented to suppress the transient oscillation. Finally, validity of the proposed FRT strategy is verified by PSCAD/EMTDC simulations.

Pole-to-ground and pole-to-metallic return conductor (MRC) short circuits are typical dc asymmetrical faults in modular multilevel converter based high voltage direct current (MMC-HVDC) grid. For secure operation, comprehensive analysis of the dc asymmetrical faults is urgently required. However, in MRC contained MMC-HVDC grid, the fault analysis is challenged by two asymmetric factors, viz. the parameter difference between dc transmission lines and the asymmetric distribution of dc limiting reactors. In light of this, a generalized dc asymmetrical fault analysis method is proposed in this paper. Firstly, with symmetrical component decomposition, the MMC- HVDC grid is decomposed into 0-, 1- and 2-modal components. The common-mode network that consists of 0- and 1-modal components is decoupled from the differential-mode network that consists of 2-modal component, which helps to reduce the analysis complexity. Then, combining the fault boundary conditions and the terminal characteristics of common-/ differential-mode networks, analytical expressions of the grid branch current and node voltage are obtained. The proposed analysis method is applicable to different dc asymmetrical faults, and is essentially a generalized form of the exiting dc fault analysis methods. Moreover, the obtained analytical expressions are verified by PSCAD/EMTDC simulation to be accurate enough to estimate the fault characteristics, and can provide insights on the fault mechanism.

In a modular multilevel converter‐based high‐voltage direct current (MMC‐HVDC) system, the dc fault ride through (FRT) control is an effective way to deal with a dc‐side pole‐to‐ground (PTG) fault. However, the setting of FRT duration brings potential hazards: 1) MMC will face the risk of “secondary short circuit” if FRT duration is short; 2) ac grid may have power angle stability issue if FRT duration is long. To avoid these hazards and provide theoretical guidance for the FRT duration setting, transient behaviour of dc fault current during the PTG FRT stage is explored in this work. Firstly, challenges of the transient analysis are summarised as non‐linearity and high‐order issues. In light of this, numerical and Hilbert‐Huang Transformation methods are introduced to evaluate the non‐linearity issue. It is found that the path of MMC from dc current to dc internal voltage is weakly non‐linear. Hence, a linear transient model is built to analyse the dc fault current. By participation factor analysis, the order of the proposed model is further reduced, so that an analytical expression of the dc fault current is approximately derived. Based on the analytical expression, regularities and mechanism of dc fault current are fully revealed. Application of the transient analysis to the setting of FRT duration is elaborated in detail. Finally, the PSCAD/EMTDC simulation verifies the validity of the proposed model and analytical expression.

The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.