In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm², and the chip size was 5.15 × 5.15 mm². The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

In this letter, we develop a compact thermal model that can predict changes in the threshold voltage and drain current because of the junction temperature, Δ _J , and its effect on a circuit performance by using circuit simulators. In addition, we propose a thermally aware layout methodology for FinFET-based digital circuits. Although heat sinks (called “via pillars”) are generally used for heat dissipation in FinFETs, these features increase the parasitic capacitance and power consumption. Therefore, we propose an optimized heat sink that is only on the critical node (showing high activity and drain-source voltage, V _DS ) and uses high metal stacks up to metal 5. With the optimization of this heat sink, we observe that the T _J of a 4-input NAND gate can be reduced about 3.2% while the oscillation frequency of an 11-stage ring oscillator can be increased about 12%, compared to conventional heat sinks.