Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

In this letter, a novel Core-Substrate Gate-All-Around (CSGAA) nanowire structure has been proposed, investigated and simulated systematically based on 3D numerical simulation. This new structure is characterized by a Core-Substrate directly connected to the substrate wafer or well which is formed by a bulk region inside the tubular channel. Comparisons are carried out between conventional Gate-All-Around (GAA) nanowire transistor and newly proposed CSGAA structure. This budding structure exhibits a maximum of four orders of magnitude of reduction in off-state current, high saturation current and low performance degradation.With the help of Core-Substrate, the CSGAA structure is able to maintain excellent performance despite geometric and structural variation. Its special structure is very suitable for the use of vertical Gate-All-Around nanowire structure, making it a promising candidate of future high performance and low power CMOS devices.

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing $\left(S{S}_{\mathrm{AVG}}\right)$ and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( $I_{\mathrm{ON}}$ ) (11.9 $\mathsf{\mu }$ A), a low OFF-state current ( $I_{\mathrm{OFF}}$ ) ( $2.85\times {10}^{-9}$ $\mathsf{\mu }$ A), and a low and steady $S{S}_{\mathrm{AVG}}$ (57.29 mV/decade), with the OFF-state current increasing by ${10}^7$ times. The GAS GAA TFET has high potential for use in low-power applications.

Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (g_m) and output conductance (g_ds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (f_T) and maximum oscillation frequency (f_max) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kk_DE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.

On the road of CMOS device continuously scaling, there are lots of challenges regarding the device structure and material engineering. GaN channel has recently been used in MOSFETs and achieved excellent performance. In this paper, we study a novel embedded gate GaN nanotube field effect transistor of 5 nm gate length with ION/IOFF as high as 106, and subthreshold swing (SS) as small as 64 mV/dec using Sentaurus TCAD simulation. The device can effectively improve subthreshold characteristics due to the GaN channel and embedded gate design. Compared with Si nanotube FET and GaN nanowire FET, GaN embedded nanotube FET exhibits low SS and high ION/IOFF at the same channel thickness. GaN embedded nanotube FET has also been determined to superior temperature adaptability and performs better in terms of threshold voltage and subthreshold characteristics compared to Si nanotube FET at the same temperature. In addition, we investigated the impact of different lengths and thicknesses of the embedded gate on the subthreshold characteristics. As the length and thickness of the embedded gate are increased, SS and ION/IOFF are improved. This excellent electrical performance demonstrates the possibility of GaN as a channel material in MOSFETs and embedded gate as an effective design to improve subthreshold characteristics, opening a new way for continued device scaling.