This paper proposes a novel method for extracting Finite State Machines (FSMs) from flattened gate-level netlist. The proposed method which employs a potential state register elimination technique and a two-level FSM separation strategy is highly applicable to control-intensive circuits. The potential state register elimination technique is based on control signal identification whereas the two-level FSM separation strategy is based on enable tree identification and the strongly connected components algorithm. To demonstrate the efficacy and to illustrate the unique features of the proposed FSM extraction method, the Synopsys DesignWare DW8051 microcontroller is used as the benchmark circuit for comparison and simulations. Results show that the proposed method reduces the complexity of the extracted FSMs in terms of number of state registers in an FSM by more than 90% as compared to the reported technique.

A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) /spl ap/0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial /spl sim/47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (/spl sim/60 /spl mu/W @1.1 V and 48-kHz sampling rate, and THD /spl ap/0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids.

Microcontrollers play a vital role in embodying intelligence into battery-powered everyday objects to realize the internet of things (IoT). The desirable attributes of such a microcontroller and the like include high energy and area efficiency, and robust error-free operation under dynamic voltage scaling (DVS), workload, process, voltage, and temperature (PVT) variation effects. In this work, a synchronous-logic ( S 8051) and a quasi-delay-insensitive asynchronous-logic ( A 8051) 8051 microcontroller core are designed and fabricated for full-range DVS from nominal VDD to deep sub-threshold. The performance of the S 8051 and A 8051 are largely comparable at nominal conditions and the entire DVS range, but differs when PVT and workload are varied. At nominal VDD , both the microcontroller cores feature comparable energy and speed, with the electromagnetic interference of the A 8051 ~ 12 dB lower and the area ~ 2 × larger than the S 8051. When DVS is applied, both the microcontroller cores feature comparable energy and speed; the S 8051 requires simultaneous adjustment of clock frequency with VDD . At wide PVT variations, up to ~ 12 × delay margins are required for the S 8051, whereas the A 8051 operates at actual speed. When the workload of both microcontrollers is varied, the A 8051 features lower energy dissipation per workload due to the exploitation of its asynchronous-logic protocols. For IoT applications that incur wide PVT and workload variations, A 8051 is more suitable due to its self-timed nature, whereas when PVT and workload variations are less severe, S 8051 is more suitable due to a smaller IC area.

We describe a 16-channel critical-like spaced, high stopband attenuation (ges60 dB, 109thtimes16-order), micropower (247.5 muW@1.1 V, 0.96 MHz), small integrated circuit (IC) area (1.62 mm²@0.35-mum CMOS) finite impulse response filter bank core for power-critical hearing aids. We achieve the low-power and small IC area attributes by our proposed common pre-computational unit to generate a set of pre-calculated intermediate values that is shared by all 16 channels. We also take advantage of the consecutive zeros in the coefficients of the filter channels, allowing the multiplexers therein to be simplified. We show that our design is very competitive compared to reported designs, and with the advantages of higher stopband attenuation and linear phase frequency response. Compared to a design using the usual approach, our design features 47% lower power dissipation and 37% smaller IC area

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ~5.6 and ~10 per adder in the adder block in conventional 16times16-bit and 32times32-bit designs respectively to ~2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16times16-bit design dissipates ~32% less power, is ~20% slower but has ~20% better energy-delay-product (EDP) than conventional 16times16-bit multipliers. Our 32times32-bit design is estimated to dissipate ~53% less power, ~29% slower but is ~39% better EDP than the conventional general multiplier