We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO ₂ films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance R _sh of 2 Ω, followed by the deposition of Nb/Al-AlO _x /Nb trilayer Josephson-junction. The target critical current density J _c was set at 6 kA/cm ² . Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.

We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm ² Nb/AlO _x /Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (I _C ), bias current (I _bias ), and inductance satisfied minimal margin requirements. Critical margins of I _C and I _bias were then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the I _C . The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.

We address all round development of the standard cell library including simulation, layout, and testing. We present a new circuit analysis scheme based on Monte-Carlo simulations and process corners. Using a phase modulation decoder as an example circuit, we identify weak spots in the design that was originally optimized for parameter margins. To support static timing analysis for very high complexity circuits, we describe the timing characterization of library cells as a function of its load, and demonstrate digital timing verification with timing back-annotation using Verilog hardware descriptive language. For the layout of library cells, we present architecture for the dual RSFQ/ERSFQ standard cell library for the MIT-LL, 10 kA/cm ² , SFQ4EE and SFQ5EE processes. Testing and characterizing hundreds of library cells, including unique cells and their layout variations, is a challenge. For efficient characterization of the digital cells, we have developed an NDRO cell-based multiplexing scheme that lets us characterize hundreds of cells on a single chip. For better model-to-hardware correlation, we have implemented a differential delay measurement scheme using ring oscillators that facilitates timing characterization of the synchronous and asynchronous cells. We also report design and measurement of statistical variations for the critical current of decision-making pair of junctions.

$\rm Nb/Al-AlO_x/Nb$ Josephson junctions are widely used in SQUIDs and Rapid Single Flux Quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in $\RM Nb/Al-AlO_x/Nb$ trilayer based Josephson junctions is a critical factor af-fecting their qualities. In this work, we develop a multi-step sput-tering process to prepare Nb films with different combinations of stress and roughness for investigating the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but dif-ferent stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of $\rm Nb/Al-AlO_x/Nb$ Josephson junctions and larger film roughness has a positive effect on junc-tion quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated $\rm Nb/Al-AlO_x/Nb$ Jo-sephson junctions with a high quality factor characterized by $R_{sg}/R_N$ (30 averagely). The minimum size of junctions was 1 μm.

We have developed a 6-kA/cm superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density J _c , normal-state resistance R _n and actual sizes of Josephson junctions, the sheet resistance of Mo resistor R _sh , and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.