Over the past decade, the design of low-power processors is a primary requirement of emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore, there has been renewed interest in asynchronous circuits for their low-power consumption and robustness. However, one of the main obstacles is the lack of commercial EDA tool support, which makes asynchronous design takes time and is not well-suited for industrial adoption. This brief proposes a new methodology for implementing asynchronous phase-decoupled click-based circuits with traditional EDA tools. To perform static timing analysis both in the control and data paths, we capture asynchronous event propagation via generated clocks. Moreover, we present an adaptive pipeline asynchronous RISC-V processor implemented on the FPGA, Xilinx ZCU102 board. The implementation result shows that the asynchronous RISC-V processor achieves a 3× dynamic power improvement against the synchronous one with a similar resource.

Neurons are the primary building block of the nervous system. Exploring the mysteries of the brain in science or building a novel brain-inspired hardware substrate in engineering are inseparable from constructing an efficient biological neuron. Balancing the functional capability and the implementation cost of a neuron is a grand challenge in neuromorphic field. In this paper, we present a low-cost adaptive exponential integrate-and-fire neuron, called SC-AdEx, for large-scale neuromorphic systems using stochastic computing. In the proposed model, arithmetic operations are performed on stochastic bit-streams with small and low-power circuitry. To evaluate the proposed neuron, we perform biological behavior analysis, including various firing patterns. Furthermore, the model is synthesized and implemented physically on FPGA as a proof of concept. Experimental results show that our model can precisely reproduce wide range biological behaviors as the original model, with higher computational performance and lower hardware cost against state-of-the-art AdEx hardware neurons.

Large-scale neural network (NN) accelerators typically consist of several processing nodes, which could be implemented as a multi- or many-core chip and organized via a network-on-chip (NoC) to handle the heavy neuron-to-neuron traffic. Multiple NoC-based NN chips are connected through chip-to-chip interconnection networks to further boost the overall neural acceleration capability. Huge amounts of multicast-based traffic travel on-chip or cross chips, making the interconnection network design more challenging and become the bottleneck of the NN system performance and energy. In this article, we propose coupling intrachip and interchip communication techniques, called NeuronLink, for NN accelerators. Regarding the intrachip communication, we propose scoring crossbar arbitration, arbitration interception, and route computation parallelization techniques for virtual-channel routing, leading to a high-throughput NoC with a lower hardware cost for multicast-based traffic. Regarding the interchip communication, we propose a lightweight and NoC-aware chip-to-chip interconnection scheme, enabling efficient interconnection for NoC-based NN chips. In addition, we evaluate the proposed techniques on a four connected NoC-based deep neural network (DNN) chips with four field-programmable gate arrays (FPGAs). The experimental results show that the proposed interconnection network can efficiently manage the data traffic inside DNNs with high-throughput and low-overhead against state-of-the-art interconnects.

Spiking neural network (SNN), known as the third generation of neural networks, is attracting more and more researchers' attention because of its high energy efficiency. However, due to the spatiotemporal characteristics, SNN involved a few complicated computations such as exponential function and logarithmic function, making it hard to implement on hardware. In this brief, we propose a SNN processor, which balances the trade-offs between cost and performance. In terms of cost, through software and hardware co-design, a high-robustness SNN model with 2-bit weights and a novel synapse delay management mechanism are adopted to reduce memory utilization. In terms of performance, a spike encoder and a VFA (Vote-For-All) decoder are used to reduce latency and improve inference accuracy respectively. We implement the design on the Xilinx ZCU102 FPGA board and apply it to the MNIST handwritten digit classification, which achieves 90.53% classification accuracy. Compared to a previous proposed SNN processor of a similar neuron scale, our design achieves a 156 × inference speed-up and consumes 0,32 × hardware resources.

Deep Neural Networks (DNNs) are revolutionizing machine learning, with unprecedented accuracy on many AI tasks. Energy-efficient neural acceleration is crucial in broadening DNN applications in cloud and mobile end devices. However, power-hungry clock networks limit the energy-efficiency of DNN accelerators. In this work, we propose a novel DNN hardware accelerator, called the Asynchronous Neural Network Processor (AsNNP). At the heart of AsNNP is a scalable hierarchy matrix multiply unit, with bit-serial PEs working in parallel. It replaces the global clock networks with asynchronous handshake protocols to realize the synchronization and communication between each part, minimizing the dynamic power. Meanwhile, a fine-grain asynchronous pipeline based on Weak-Conditioned Half-Buffer (WCHB) is introduced to pipe successive computations in a data-driven manner, i.e., once data arrives computation begins, maximizing the throughput. These techniques enable AsNNP to work in a fully data-driven asynchronous communication fashion with optimized energy-efficiency. The proposed accelerator is implemented with Quasi-Delay-Insensitive (QDI) clockless logic family and evaluated in a 65nm process. Compared with the synchronous baseline, simulation results show that AsNNP offers 2.2X higher equivalent frequency and 1.59X lower power. Compared with state-of-the-art DNN accelerators, AsNNP shows 1.17X-4.97X energy-efficiency improvement.

The brain’s ability to anticipate future events is crucial for intelligent behavior. However, when deploying the capability to edge devices, there are huge challenges in terms of resources and power consumption. The main obstacle is the state-of-the-art neuromorphic hardware with Spike Timing Dependent Plasticity (STDP) learning rule requires significant computation for synaptic weight updates and memory to store intermediate synaptic weights. In this paper, we proposed an approximate Spiking Neural Network (SNN) accelerator with on-chip Predictive Learning Rule (PLR), which is a biological behavior observed in the brain, named SC-PLR. In SC-PLR, the principles of predictive processing are extended to enable neurons to learn temporal sequences and anticipate future events with minimum synaptic weight updates, while stochastic computing is leveraged to balance the hardware cost, energy efficiency, and accuracy. Simulation results demonstrate that PLR-based SNNs effectively enable adaptive and anticipatory behavior in robotics and decision-making scenarios. Additionally, FPGA implementation results show that the proposed SC-PLR outperforms stateof- the-art STDP-based SNN designs in terms of resources and power consumption. Specifically, our design achieves significant resource savings, including 77.3% Look-Up Table (LUT), 79.4% Flip-Flop (FF), and 56.4% Block RAM (BRAM) resources, and power consumption reduction by 32%. ^{1 1}The code is available at https://github.com/lucy-weizi/SC-PLR.