Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active NPC inverter is discussed in this paper, which consists of only 6 switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped PWM is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method.

The neutral-point voltage unbalance problem holds back the extensive application of neutral-point clamped (NPC) multilevel converters with more than three voltage levels in industry. Traditional phase-disposition PWM (PDPWM) or nearest-three-vectors (NTV) modulation cannot achieve the voltage balance over the full modulation indexes and load power factors when the voltage level is higher than three. To solve this problem, a novel generalized carrier-based PWM method named carrier-overlapped PWM (COPWM) for NPC multilevel converters is proposed in this paper, which is proved to satisfy the volt-second balance principle. With this modulation method, the average values of all the neutral-point currents equal to zero in a fundamental period, and so all the dc-link capacitor voltages can be naturally balanced in the ideal and steady-state conditions. In order to simplify its implementation, an equivalent multi-reference modulation method with only one triangular carrier is also derived. Simulation and experimental results on a five-level diode-clamped inverter are presented to verify the proposed modulation method.

Neutral-point voltage imbalance is one of the main problems of five-level neutral-point clamped (NPC) inverters that impedes their industrial application. In order to solve this problem, a closed-loop neutral-point voltage balancing method based on carrier-overlapped PWM (COPWM) is proposed in this paper. The four DC-link capacitor voltages are balanced by three steps: voltage balancing between the two outer capacitors, voltage balancing between the two inner capacitors, and voltage balancing between the two inner and the two outer capacitors. The relationship between the neutral-point currents and the reference voltage is studied, and the top and the bottom DC-link capacitor voltages are balanced by zero-sequence voltage injection. The two inner capacitor voltages are balanced by adjusting the width of switching signals. Simulation and experimental results are presented to confirm the validity of this method.

Neutral-point clamped multilevel converters with more than three voltage levels are hard to balance the DC-link capacitor voltages, which limits their application in industry. In order to solve the neutral-point potential balancing problem of four-level neutral-point clamped converters, a novel carrier-overlapped PWM method is proposed in this letter, which satisfies the volt-second balance principle and can achieve the natural voltage balance of three DC-link capacitors under ideal and steady states. Experimental results are presented to confirm the validity of this PWM method.

This paper proposes a fast repetitive control (FRC) scheme with harmonic correction loops for the three-phase three-wire shunt active power filter (APF) applied in weak power grid. The FRC scheme consists of a repetitive control loop which is designed in the synchronous rotational frame (SRF) and a fractional delay (FD) filter for approximating the fractional delay caused by the fixed sampling rate. It can significantly improve the dynamic performance for the harmonic compensation. In weak grid situation, the grid frequency, voltage and then harmonic currents would vary rapidly with disturbances. A cumulative error cancellation loop is introduced into the FRC to improve the harmonic detection accuracy when grid frequency drifts. And the harmonic correction loops are proposed to correct the harmonic references with selected orders when they vary rapidly with the grid voltage. With such loops, the compensation precision of the shunt APF can be highly improved. Simulation and experiment results verified the effectiveness of the proposed scheme.