This article presents the utilization of the chemical–mechanical polishing (CMP) method to fabricate high-performance N-polar GaN/AlGaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) through layer transfer technology. The nucleation and buffer layers were removed via CMP to attain a pristine N-polar GaN surface with elevated smoothness, featuring a low root-mean-square (RMS) roughness of 0.216 nm. Oxygen, carbon, and chlorine impurity elements content were low after the CMP process, as detected via X-ray photoelectron spectroscopy (XPS). The electrical properties of N-polar HEMTs fabricated via CMP exhibited a sheet resistance (R_sh) of 244.7 Ω/sq, a mobility of 1230 cm²/V·s, and an n_s of 2.24 × 10¹³ cm⁻². Compared with a counter device fabricated via inductively coupled plasma (ICP) dry etching, the CMP devices showed an improved output current of 756.1 mA/mm, reduced on-resistance of 6.51 Ω·mm, and a significantly reduced subthreshold slope mainly attributed to the improved surface conditions. Meanwhile, owing to the MIS configuration, the reverse gate leakage current could be reduced to as low as 15 μA/mm. These results highlight the feasibility of the CMP-involved epitaxial layer transfer (ELT) technique to deliver superior N-polar GaN MIS-HEMTs for power electronic applications.

This work presents a comparative study of GaN metal-insulator-semiconductor high-electron-mobility-transistors (MIS-HEMTs) employing LPCVD-SiNx/ALD-AlN or PEALD-SiO2/ALD-AlN dielectric stacks. The SiNx/AlN MIS-HEMTs exhibit a minimal threshold voltage shift ( $\Delta {V}_{\text {TH}}$ ) of −0.24 V with an on/off current ratio up to $10^{{8}}$ under $150~^{\circ }$ C, compared to $\Delta {V}_{\text {TH}}=2.0$ V for SiO2/AlN MIS-HEMTs. Under gate bias stress, SiNx/AlN devices show $\Delta {V}_{\text {TH}}$ of −0.90 V (positive) and −0.45 V (negative), versus −1.75 and 3.31 V for SiO2/AlN devices. After maintaining $10^{{4}}$ s of off-state drain-bias stress, SiNx/AlN MIS-HEMT achieves a small $\Delta {V}_{\text {TH}}$ of −0.45 V. The improved stability is attributed to the better interface quality of SiNx/AlN stack, enabled by the low-pressure chemical vapor deposition (LPCVD) process and nitrogen-rich environment. These findings underscore the potential of LPCVD-SiNx/ALD-AlN dielectric stacks in advancing GaN MIS-HEMTs for high-performance and reliable power switching applications.

This work proposes a novel gate stack with hydrogen (H) plasma treatment to improve the stability of p-channel field effect transistors (p-FETs). The threshold voltage (V _TH) of this device is −4.82 V, achieving normally-off operation, with exhibiting an I _on/I _off ratio of 10⁶ and a low off-state leakage current of −10⁻⁷ mA mm⁻¹ at V _GS = 2 V. The H plasma-treated gate stack significantly stabilizes the V _TH of GaN p-FETs, exhibiting minimal variations of 0.14 V and 0.15 V under negative (−5 V) and positive (5 V) gate voltages, respectively. H plasma treatment technology optimizes the sub-gate interface and enhances the threshold voltage stability of the device, guaranteeing the stable application of p-FETs in logic circuits.