An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-μH off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-μm CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

A 13.56 MHz wireless power transfer system with a 1X/2X reconfigurable resonant regulating (R ³ ) rectifier and wireless power control for biomedical implants is presented. Output voltage regulation is achieved through two mechanisms: (1) a local PWM loop at the secondary side controls the duty cycle of mode-switching of the rectifier between the 1X and 2X modes; and (2) a global control loop obtains the mode-switching information from the secondary side and send it back to the primary side through the wireless channel and adjusts the transmitter power of the primary coil to adapt to load and coupling variations. Two novel backscattering uplink techniques are proposed for fast and energy-efficient data feedback. The first is for general data transmission using Manchester code; and the second is for fast duty cycle feedback to cater for fast load-transient responses. Stability analysis of the entire system with the two control loops is also presented. The primary transmitter and the secondary R ³ rectifier are fabricated in 0.35 μm CMOS process with the digital control circuits implemented using FPGA. The measured maximum received power and receiver efficiency are 102 mW and 92.6%, respectively. For load transients, the overshoot and the undershoot are approximately 110 mV and the settling times are less than 130 μs.

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

This paper presents a single-inductor multiple-output (SIMO) converter operating in pseudo-continuous conduction mode (PCCM) and/or discontinuous conduction mode (DCM). With the proposed freewheel switching control, this converter can handle large load currents with a much smaller current ripple, while retaining low cross regulation. It can also work in DCM for high efficiency at light loads. A prototype of a single-inductor dual-output (SIDO) boost converter was fabricated with a standard 0.5-μm CMOS n-well process. The two outputs are regulated at 2.5 and 3.0 V, respectively. At an oscillator frequency of 1 MHz, the efficiency reaches 89.4% at a total output power of 320 mW. Compared with prior designs, both current and voltage ripples are reduced. This design can be extended to have multiple outputs and for different types of dc-dc conversions, or be applied to single-output converters for fast transient response.

A low-loss CMOS full-wave active rectifier is presented. It consists of two dynamically biased and symmetrically matched active diodes each realized by an nMOS switch driven by a 2-ns voltage comparator with reverse-current control. With a load of 1.8-kOmega, the rectified dc voltage is 3.22 V and 1.2 V for a 13.56 MHz ac sinusoidal input voltage of 3.5 V and 1.5 V respectively. It is fabricated in a 0.35-mum CMOS process with an active area of 0.0055 mm ², with no low-threshold devices and on-chip passive components

CMOS circuits consume power during the charging and discharging of capacitances. Reducing switching activity then, saves power in embedded processors. The authors' two-pronged attack uses Gray code addressing and cold scheduling to eliminate bit switches.