The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using AI in power-limited applications. In this paper, a BNN hardware accelerator is proposed. The proposed approach is based on a novel nonvolatile XNOR/XOR circuit designed using the magnetic tunnel junction (MTJ) and gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) devices. The nonvolatility of the proposed design leads to the elimination of external memory access that significantly decreases the data transmission delay and power dissipation. Moreover, it consumes low energy, which is very critical in battery-operated devices. Furthermore, the combinational read circuitry of the proposed design leads to high robustness to process variations. According to the simulation results, our proposed design has a logical error rate of 0.0164%, which is negligible and offers a significantly high network accuracy even in the presence of significant process variations. Our proposed hardware accelerator provides at least 13%, 29%, and 41% improvements regarding power, power delay product (PDP), and area compared to its state-of-the-art counterparts.

This paper proposes a reliable integrated binary synapse and neurons for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of the magnetic tunnel junction ( MTJ ) and the unique features of the carbon nanotube field-effect transistor ( CNTFET ), the proposed design in this paper does not require external memory to store weights and also consumes low static power. Also, due to the proposed circuit structure that did not use sequential parts, the proposed circuit is immune to soft error. Because in binary neural networks, weights are limited to two values of ‘-1’ and ‘1’, the occurrence of soft errors dramatically reduces the accuracy of the network. Simulation results indicate that the proposed design in this paper consumes at least 9% lower power, occupies 34% lower area, and offers a 49% lower power delay area product ( PDAP ). Also, Monte-Carlo simulations have been performed to study the effect of the process variation on the network. The result of the Monte-Carlo simulations shows that the proposed neuron has no logical error in 10000 simulations. Consequently, the accuracy of the network utilizing by the proposed neuron is equal to the software-implemented network and does not decrease even in the presence of process variations.

This paper proposes an SEU-hardened task-scheduling logic in memory XNOR/XOR neuron and synapse circuits. Using C-element and magnetic tunnel junction enhances immunity against single event upset injection to the design. Also, using logic in memory architecture eliminates the need to access external memory and decreases power and delay. Furthermore, using the carbon nanotube field-effect transistor leads to lower leakage and static current caused by higher gate control in these transistors. Compared to the state-of-the-art counterparts, the proposed design offers at least 31%, 17%, and 3% improvement regarding power, power delay product, and power delay area product

Signed multiplication is crucial for performing arithmetic operations with positive and negative numbers. It has applications in signal processing, digital image processing, communication, cryptography, neural network hardware accelerators, and more. Until today, to multiply signed numbers, the data are often converted to unsigned format, and the sign is added to the final product. This method imposes high hardware requirements for data conversion and presents challenges in designing approximate multipliers. This paper proposes a novel method for designing approximate signed multipliers that eliminate the need for data conversion, thereby reducing the overall hardware requirement while maintaining accuracy. Comprehensive evaluations at the system level using MATLAB and circuit-level performance analysis using HSPICE demonstrate that the proposed approach offers a successful trade-off between area overhead, power consumption, and accuracy. The achieved trade-off makes the proposed method a promising solution for optimizing digital circuits in various applications such as artificial intelligence and image processing.

Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages.

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T.