Deep learning (DL) reliability is becoming a growing concern, and efficient reliability assessment approaches are required to meet safety constraints. This article presents a survey of the main DL reliability assessment methodologies, focusing mainly on fault injection techniques used to evaluate DL resilience.

Convolutional Neural Networks (CNNs) are currently one of the most widely used predictive models in machine learning. Recent studies have demonstrated that hardware faults induced by radiation fields, including cosmic rays, may significantly impact the CNN inference leading to wrong predictions. Therefore, ensuring the reliability of CNNs is crucial, especially for safety-critical systems. In the literature, several works propose reliability assessments of CNNs mainly based on statistically injected faults. This work presents a software emulator capable of injecting real faults retrieved from radiation tests. Specifically, from the device characterisation of a DRAM memory, we extracted event rates and fault models. The software emulator can reproduce their incidence and access their effect on CNN applications with a reliability assessment precision close to the physical one. Radiation-based physical injections and emulator-based injections are performed on three CNNs (LeNet-5) exploiting different data representations. Their outcomes are compared, and the software results evidence that the emulator is able to reproduce the faulty behaviours observed during the radiation tests for the targeted CNNs. This approach leads to a more concise use of radiation experiments since the extracted fault models can be reused to explore different scenarios (e.g., impact on a different application).

Embedded processors have been used in a diversity of applications, such as consumer electronics, home appliances, and automation systems. Another area that embedded processors can be adopted is space systems, which demand faulttolerant components to deal with the environmental hostility. This work presents a low-cost fault-tolerant implementation of the RISC-V architecture, an emerging open industry standard for the building of embedded processors. The proposed implementation employs physical and information redundancy to reduce error propagation, with competitive silicon and power overheads when comparing with other RISC-V implementations.

This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyväskylä, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyväskylä. In these irradiation tests, stuck bits originating from electron-induced single-event effects (SEEs) were found, as well as single bit-flips from single electrons. To the best knowledge of the authors, this is the first time that stuck bits from single-electron events have been reported in the literature. It is argued in the article that the single-event bit-flips and stuck bits are caused by the same damage mechanism, which would be large displacement damage clusters, and that the two different fault modes represent different amounts of damage to the memory cell. After a large particle fluence, a rapid increase in the error rate was observed, originating from the accumulation of smaller displacement damage clusters in the memory cells. The 110-nm memory was a candidate component to fly on the European Space Agency (ESA) JUpiter ICy moons Explorer (JUICE) mission, so the SEE cross section as a function of electron energy was compared to the expected electron environment encountered by JUICE to estimate the error rates during the mission.

In this study, static and dynamic test methods were used to define the response of a self-refresh DRAM under thermal neutron irradiation. The neutron-induced failures were investigated and characterized by event cross-sections, soft-error rate and bitmaps evaluations, leading to an identification of permanent and temporarily stuck cells, block errors, and single-bit upsets.