This paper reports the first experimental results obtained on a Single Photon Avalanche Diode (SPAD) implemented, in a 28nm FDSOI CMOS technology. The main originality relies on the integration of the SPAD below the buried oxide with the logic on-top in the thin silicon layer, providing an intrinsic 3D stack. The expected benefits are a much higher fill factor with embedded high performance and low power electronics. A test-chip has been fabricated with the commercial STMicroelectronics CMOS28FDSOI technology without any design rule violation nor process customization. SPAD breakdown has been investigated with electroluminescence cartography and breakdown voltage measurements. Afterwards, first dark count rate measurements are reported according to temperature and excess bias. To our knowledge, it is the first demonstration of SPAD devices in a FDSOI CMOS technology. Based on these encouraging results, the study will be pursued for more statistical data acquisition and for SPAD characterization under illumination.

Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

The development of metallic single-electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions (TJs). These TJs should insure high-ON current, low-OFF current, and low capacitance. We propose an engineered TJ based on multidielectric stacking. A number of high-k and low-k materials were considered to optimize the TJ's characteristics. The optimized TJ is proven to increase the ION current and the I _ON /I _OFF ratio in a double-gate SET. Using TiO ₂ plasma oxidation and Al ₂ O ₃ atomic layer deposition, an SET proof of concept, with a double layer TJ, was fabricated and characterized.