The convergence of edge computing systems with Field-Programmable Gate Array (FPGA) technology has shown considerable promise in enhancing real-time applications across various domains. This paper presents an innovative edge computing system design specifically tailored for pavement defect detection within the Advanced Driver-Assistance Systems (ADASs) domain. The system seamlessly integrates the AMD Xilinx AI platform into a customized circuit configuration, capitalizing on its capabilities. Utilizing cameras as input sensors to capture road scenes, the system employs a Deep Learning Processing Unit (DPU) to execute the YOLOv3 model, enabling the identification of three distinct types of pavement defects with high accuracy and efficiency. Following defect detection, the system efficiently transmits detailed information about the type and location of detected defects via the Controller Area Network (CAN) interface. This integration of FPGA-based edge computing not only enhances the speed and accuracy of defect detection, but also facilitates real-time communication between the vehicle’s onboard controller and external systems. Moreover, the successful integration of the proposed system transforms ADAS into a sophisticated edge computing device, empowering the vehicle’s onboard controller to make informed decisions in real time. These decisions are aimed at enhancing the overall driving experience by improving safety and performance metrics. The synergy between edge computing and FPGA technology not only advances ADAS capabilities, but also paves the way for future innovations in automotive safety and assistance systems.

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm² using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.