Chenyun Pan

Prof. Chenyun Pan

Electrical Engineering, The University of Texas at Arlington, Arlington, Massachusetts, USA
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Academic Career Length

15Years (2012-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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6 December 2013 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
Chenyun PanChenyun Pan
Chenyun Pan
ANAzad Naeemi
Azad Naeemi
To suppress the impact of size effects on sub-20 nm wide wires, a novel aluminum-copper hybrid interconnect architecture is proposed and its potential performance has been quantified. Al wires offer lower resistivities at nanoscale dimensions because they do not need diffusion barriers, and size effects are less prominent in them due to their smaller bulk mean free path. However, their current conduction capacity is substantially lower than that of Cu wires. To get around this limitation, this letter proposes a hybrid interconnect technology to replace only short narrow local signal wires by Al wires. This scheme takes advantage of the fact that signal wires conduct bi-directional currents and are therefore virtually immune to electromigration. The improvement in chip clock frequency is predicted to be between 50% and 100% for the 7 nm technology node.
15 January 2018 in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Verified
Journal Article
Open access
Chenyun PanChenyun Pan
Chenyun Pan
ANAzad Naeemi
Azad Naeemi
The latest results of benchmarking research are presented for a variety of beyond-CMOS charge- and spin-based devices. In addition to improving the device-level models, several new device proposals and a few majorly modified devices are investigated. Deep pipelining circuits are employed to boost the throughput of low-power devices. Furthermore, the benchmarking methodology is extended to interconnect-centric analyses and non-Boolean logic applications. In contrast to Boolean circuits, non-Boolean circuits based on the cellular neural network demonstrate that spintronic devices can potentially outperform conventional CMOS devices.
24 August 2023 in IEEE Transactions on Electron Devices
Verified
Journal Article
Closed access
HLHsiao-Hsuan Liu
Hsiao-Hsuan Liu
PSPieter Schuddinck
Pieter Schuddinck
ZPZhenlin Pei
Zhenlin Pei
LVLynn Verschueren
Lynn Verschueren
HMHans Mertens
Hans Mertens
FCFrancky Catthoor
Francky Catthoor
Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate devices, resulting in increased bitline (BL) and wordline (WL) capacitances ( $\textit{C}_{\text{BL}}$ and $\textit{C}_{\text{WL}}$ ) compared to nonstacked SRAMs. Previous research has reported that the higher parasitic capacitance hinders the power and performance gains between nodes. In this work, as a hypothetical device option aside from sequential and monolithic CFET, hybrid CFET is introduced in SRAM design with the features of double-sided interconnect design in 3-Å-compatible technology (A3). To assess its potential value in future SRAM roadmap, a comprehensive design technology co-optimization (DTCO) “what-if analysis” has been conducted. Hybrid CFET enables relaxation of metal width and shorter via connections in SRAM design compared to previous approaches. Therefore, A3 hybrid CFET SRAM can provide up to 41%, 25%, 35%, 32%, and 45 mV improvements of $\textit{R}_{\text{WL}}$ , $\textit{C}_{\text{BL}}$ , $\textit{C}_{\text{WL}}$ , read speed, and write margin, respectively, compared to sequential and monolithic counterparts. Moreover, it also exhibits 77% energy–delay–area product enhancement compared to 14-Å-compatible nanosheet technology at the macro level (128-MB cache). These compelling results motivate further research and development of the process flow for hybrid CFET devices in SRAM technology in the future.
29 November 2016 in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Verified
Journal Article
Open access
Chenyun PanChenyun Pan
Chenyun Pan
ANAzad Naeemi
Azad Naeemi
This paper presents a uniform benchmarking methodology for non-Boolean computation based on the cellular neural network (CNN) for a variety of beyond-CMOS device technologies, including charge-based and spintronic devices. Three types of CNN implementations are investigated using analog, digital, and spintronic circuits. Monte Carlo simulations are performed to quantify the impact of the input noise, thermal noise, and the number of bits representing the weights of synapses on the overall recall probability and delay. The results demonstrate that the recall probability improves significantly as the number of synapses increase. Using a 4-b resolution for synapse weights provides the best tradeoff between the required numbers of synapses and synapse bits for a target recall rate. Finally, three types of CNN implementations with various device technologies are benchmarked for a given input noise and recall accuracy target. It is shown that spintronic devices are promising candidates to implement CNNs, where up to 3× energy-delay product improvement is predicted in domain wall devices compared to its conventional CMOS counterpart.
21 January 2015 in IEEE Electron Device Letters
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Journal Article
Closed access
Chenyun PanChenyun Pan
Chenyun Pan
ANAzad Naeemi
Azad Naeemi
As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch.
11 November 2015 in IEEE Transactions on Electron Devices
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Journal Article
Closed access
DPDivya Prasad
Divya Prasad
ACAhmet Ceyhan
Ahmet Ceyhan
Chenyun PanChenyun Pan
Chenyun Pan
ANAzad Naeemi
Azad Naeemi
Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance.