Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).

A 60-GHz active microstrip antenna design comprising a three-stage pseudomorphic high electron mobility transistor amplifier integrated with a high gain antenna on an alumina substrate is presented. The amplifier has 18-dB gain and is ribbon bonded to the substrate on which the antenna is defined. The antenna is a microstrip array antenna with a simple etched pattern for producibility at high frequencies. Two antenna layouts are designed, for different coverage areas: a single array having 13.4-dBi directivity and a double array with 14.6-dBi directivity. Antenna losses are approximately 1-2 dB, giving antenna gains of about 12 and 13 dBi, respectively. Mechanical simplicity is achieved with this design, and unnecessary transitions are avoided. Measurements are performed on amplifier and antenna separately, as well as on the integrated design. Amplifier chips with and without benzocyclobutene passivation are fabricated and measured for comparison

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15mum (f_T~ 120 GHz/f _MAX> 200 GHz) GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs together with work on packaging (e.g., flip-chip) and system measurements. Compared to the first generation of the designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half the DC power consumption. The system operates with a LO signal in the range of 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO multiplier chain, resulting in an IF center frequency of 2.5 GHz. Packaging and interconnects are discussed and as an alternative to wire bonding, flip-chip assembly tests are presented and discussed. System measurements are also described where bit error rate (BER) and eye diagrams are measured when the presented TX and RX MMICs transmits and receives a modulated signal. A data rate of 1.5 Gb/s with simple ASK modulation was achieved, restricted by the measurement setup rather than the TX and RX MMICs. These tests indicate that the presented MMICs are especially well suited for transmission and reception of wireless signals at data rates of several Gb/s

Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 ¿m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (×6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the ×6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.

A grid array antenna working around 145 GHz is proposed in this paper. The antenna is built on liquid crystal polymer (LCP) and designed for the D-band antenna-in-package application. The intrinsic softness of the LCP material is a limiting factor of the antenna's aperture size. A 0.5-mm-thick copper core is used to compensate. By doing this, the rigidness of the antenna is effectively improved, compared with an antenna without the copper core. Wet etching is used to realize the patterns on the top and bottom conductor. Compared with a low-temperature cofired ceramic counterpart, we obtain a considerable cost reduction with acceptable performance. The proposed antenna has an impedance bandwidth of 136-157 GHz, a maximum gain of 14.5 dBi at 146 GHz, and vertical beams in the broadside direction between 141 and 149 GHz. The fabrication procedures of the antennas are introduced, and a parametric study is carried out, which shows the antenna's robustness against fabrication tolerances, such as the not-well-controlled etching rate and the substrate surface roughness. This makes the antenna a promising solution for mass production.

The development of a system simulation platform for adaptive cruise control (ACC) radar working at 77 GHz is presented. The simulation platform allows us to test different radar architectures, modulation formats and detection algorithms as well as to simulate different scenarios, which improves the decision-making before and during the hardware development.