In recent years, garbage classification has become a hot topic in China, and legislation on garbage classification has been proposed. Proper garbage classification and improving the recycling rate of garbage can protect the environment and save resources. In order to effectively achieve garbage classification, a lightweight garbage object detection model based on deep learning techniques was designed and developed in this study, which can locate and classify garbage objects in real-time using embedded devices. Focusing on the problems of low accuracy and poor real-time performances in garbage classification, we proposed a lightweight garbage object detection model, YOLOG (YOLO for garbage detection), which is based on accurate local receptive field dilation and can run on embedded devices at high speed and with high performance. YOLOG improves on YOLOv4 in three key ways, including the design of DCSPResNet with accurate local receptive field expansion based on dilated–deformable convolution, network structure simplification, and the use of new activation functions. We collected the domestic garbage image dataset, then trained and tested the model on it. Finally, in order to compare the performance difference between YOLOG and existing state-of-the-art algorithms, we conducted comparison experiments using a uniform data set training model. The experimental results showed that YOLOG achieved $A{P}_{0.5}$ of 94.58% and computation of 6.05 Gflops, thus outperformed YOLOv3, YOLOv4, YOLOv4-Tiny, and YOLOv5s in terms of comprehensive performance indicators. The network proposed in this paper can detect domestic garbage accurately and rapidly, provide a foundation for future academic research and engineering applications.

This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in a 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is a single-channel bidirectional (1Tx + 1Rx) optical transceiver ASIC, including a Laser Driver (LD) module and a Limiting Amplifier (LA) module. It would drive the Vertical Cavity Surface Emitting Laser (VCSEL) of Transmitter Optical Sub-Assembly (TOSA) and receive signals from Photo Diode (PD) of Receiver Optical Sub-Assembly (ROSA), respectively. In the LDLA14, a novel structure of capacitive coupling pre-emphasis is proposed in the output driver of LD to obtain peaking effect without sacrifice the modulation current swing. A shared inductor technology and a Continuous Time Linear Equalizer (CTLE) pre-emphasis structure are added in the output buffer of LA to improve the quality of the output eye diagram. The dimension of LDLA14 is 1.5 mm × 1.3 mm, and the power consumption is 178 mW. The Peak-to-Peak Jitter (PPJ) and Root-Mean-Square Jitter (RMSJ) of the 14 Gbps optical eye diagram of LD in the Tx direction are 22.5 ps and 3.5 ps, respectively. The PPJ and RMSJ of the 14 Gbps electrical eye diagram of LA in the Rx direction are 23.1 ps and 4.7 ps, respectively. The BER tests have been conducted in Tx, Rx directions and the Tx-Rx loop condition, and the BER less than 10⁻¹² is achieved in all tests.

This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. It consists of an equalizer stage, a limiting amplifier stage and an output driver stage. The equalizer stage uses the CTLE structure to compensate the high frequency losses at the PCB traces, bonding wires and input pads. To meet both the gain/bandwidth requirements and the area restriction, the limiting amplifier stage adopts the inductor-shared peaking technology. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed. This ASIC has been integrated with the VCSEL array in a customized optical module for the optical test. The test results show the wide-open 14 Gbps optical eye diagram with a measured RMS jitter of 2.7 ps and a peak-to-peak jitter of 17.4 ps, respectively.