Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device’s electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence.
N-type organic field-effect transistors have suffered from poor environmental instability. Here, we report that, by using nickel (Ni) instead of the commonly used gold (Au) as contact electrodes, n-type polymer transistors showed much improved stability upon annealing in nitrogen and exposure to air. In particular, Au-contacted devices exhibited pronounced ambipolar conduction whereas Ni-contacted devices retained fairly good unipolar properties. The results are important to build stable n-type polymer transistors at low cost.
28 May 2024 in Journal of Materials Science: Materials in Electronics
Recently, 3D packaging has been regarded as an important technical means to continue Moore’s Law. However, excessive stacking will increase the longitudinal dimension, and one chip with high-density bondings packaging is still needed. Thus, it naturally places higher demand on thermal cycling reliability due to the decreased joint size to satisfy high-density packaging. In this work, the nano-Al2O3 (1 wt.%) modified Sn-1 wt.% Ag-0.5 wt.% Cu low-Ag solder was applied as a solder sample to evaluate the associated thermal cycling reliability. The investigated results revealed that the nano-Al2O3 modified solder did present enhanced thermal cycling reliability, as evidenced by the delayed microstructure coarsening and the inhibited atom inter-diffusion at interface caused by the adsorption of nano-Al2O3 on grain surfaces, and the resultant pinning effect. Worthy of note is that the potential of the newly developed nano-Al2O3 modified solder for high-density packaging applications (e.g., BGA, QFN, and CCGA) was evaluated based on the Finite Element Modeling.
Conventional cooling schemes that rely on rigid heat-sink-to-die coupling in vertical stacks fail to track the dynamic, non-uniform heat map of high-performance artificial-intelligence (AI) chips employing chiplet-based heterogeneous integration, giving rise to local hot spots. To eliminate this mismatch, we present a leaf-vein-inspired fractal microchannel tailored for such AI processors. Its hierarchical bifurcation–confluence topology adaptively reshapes the flow field, delivering ultra-low thermal resistance, high heat-transfer coefficients, and uniform dissipation. Coupled with reconfigurable chiplet placement, the design is evaluated through FEM-based orthogonal experiments that rank the influence of coolant, channel diameter/depth, inlet/outlet position, substrate thickness, and flow rate via range analysis and Analysis of Variance (ANOVA). A machine-learned surrogate model of junction temperature is then fed to Particle Swarm Optimization (PSO) for multi-parameter optimization. When re-simulated with the optimal parameter set, the symmetric fractal network lowered the AI chip junction temperature from 127.80 °C to 30.97 °C, a 76% improvement, offering a theoretical basis for hotspot mitigation in advanced heterogeneous AI packages.