The threading dislocation density (TDD) in plastically relaxed Ge/Si(001) heteroepitaxial films is commonly observed to decrease progressively with their thickness due to mutual annihilation. However, there exists a saturation limit, known as the geometrical limit, beyond which a further decrease of the TDD in the Ge film is hindered. Here, we show that such a limit can be overcome in SiGe/Ge/Si heterostructures thanks to the beneficial role of the second interface. Indeed, we show that ${\mathrm{Si}}_{0.06}{\mathrm{Ge}}_{0.94}/\mathrm{Ge}/\mathrm{Si}\left(001\right)$ films display a TDD remarkably lower than the saturation limit of Ge/Si(001). Such a result is interpreted with the help of dislocation dynamics simulations. The reduction of TDD is attributed to the enhanced mobility acquired by preexisting threading dislocations after bending at the new interface to release the strain in the upper layer. Importantly, we demonstrate that the low TDD achieved in ${\mathrm{Si}}_{0.06}{\mathrm{Ge}}_{0.94}/\mathrm{Ge}/\mathrm{Si}$ layers is preserved also when a second, relaxed Ge layer is subsequently deposited. This makes the present reverse-grading technique of direct interest also for achieving a low TDD in pure-Ge films.

To develop a III/V wide bandgap collector concept for future SiGe heterobipolar transistor performance increase, a heterostructure growth study of GaP on pseudomorphic 4° off-oriented Si_0.8Ge_0.2/Si(001) substrates was performed. For pseudomorphic GaP/Si_0.8Ge_0.2/Si(001) heterostructure growth, critical thickness of GaP on Si and maximum thermal budget for GaP deposition were evaluated. A detailed structure and defect characterization study by x-ray diffraction, atomic force microscopy, and transmission electron microscopy is reported on single crystalline 170 nm GaP/20 nm Si_0.8Ge_0.2/Si(001). Results show that 20 nm Si_0.8Ge_0.2/Si(001) can be overgrown by 170 nm GaP without affecting the pseudomorphism of the Si_0.8Ge_0.2/Si(001) layer. The GaP layer grows however partially relaxed, mainly due to defect nucleation at the GaP/Si_0.8Ge_0.2 interface during initial island coalescence. The achievement of 2D GaP growth conditions on Si_0.8Ge_0.2/Si(001) systems is thus a crucial step for achieving fully pseudomorphic heterostructures. Anti-phase domain-free GaP growth is observed for film thicknesses beyond 70 nm.

We present the nanoheteroepitaxial growth of gallium arsenide (GaAs) on nano-patterned silicon (Si) (001) substrates fabricated using a CMOS technology compatible process. The selective growth of GaAs nano-crystals (NCs) was achieved at 570 °C by MOVPE. A detailed structure and defect characterization study of the grown nano-heterostructures was performed using scanning transmission electron microscopy, x-ray diffraction, micro-Raman, and micro-photoluminescence ( μ -PL) spectroscopy. The results show single-crystalline, nearly relaxed GaAs NCs on top of slightly, by the SiO ₂ -mask compressively strained Si nano-tips (NTs). Given the limited contact area, GaAs/Si nanostructures benefit from limited intermixing in contrast to planar GaAs films on Si. Even though a few growth defects (e.g. stacking faults, micro/nano-twins, etc) especially located at the GaAs/Si interface region were detected, the nanoheterostructures show intensive light emission, as investigated by μ -PL spectroscopy. Achieving well-ordered high quality GaAs NCs on Si NTs may provide opportunities for superior electronic, photonic, or photovoltaic device performances integrated on the silicon technology platform.

This work investigates the role of threading dislocation densities (TDD) in the low density regime on the vertical transport in Si_0.06Ge_0.94 heterostructures integrated on Si(001). The use of unintentionally doped Si_0.06Ge_0.94 layers enables the study of the impact of grown-in threading dislocations (TD) without interaction with processing-induced defects originating, e.g., from dopant implantation. The studied heterolayers, while equal in composition, the degree of strain relaxation, and the thickness feature three different values for the TDD as 3 × 10⁶, 9 × 10⁶, and 2 × 10⁷ cm⁻². Current–voltage measurements reveal that leakage currents do not scale linearly with TDD. The temperature dependence of the leakage currents suggests a strong contribution of field-enhanced carrier generation to the current transport with the trap-assisted tunneling via TD-induced defect states identified as the dominant transport mechanism at room temperature. At lower temperatures and at high electric fields, direct band-to-band tunneling without direct interactions with defect levels becomes the dominating type of transport. Leakage currents related to emission from mid-gap traps by the Shockley–Read–Hall (SRH) generation are observed at higher temperatures (>100 °C). Here, we see a reduced contribution coming from SRH in our material, featuring the minimal TDD (3 × 10⁶ cm⁻²), which we attribute to a reduction in point defect clusters trapped in the TD strain fields.

In this work, we investigate the effective background charge density in intrinsic Si0.06Ge0.94/Ge plastically relaxed heterostructures deposited on Si(001). Hall effect measurements and capacitance–voltage profiling reveal a p-type conductivity in the nominally intrinsic layer with a hole concentration in the mid 1015 cm−3 range at temperatures between 50 and 200 K. In view of the carrier freeze out that we observe below 50 K, we attribute the origin of these carriers to the ionization of shallow acceptor-like defect states above the valence band. In addition, one dominant hole trap located at mid-gap position is found by deep level transient spectroscopy. Carrier trapping kinetics measurements can be interpreted as due to a combination of point defects, likely trapped in the strain field of extended defects, i.e., the threading dislocation.