In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the “current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs” structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a −3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10⁻¹³, demonstrating good performance.

This paper presents the effective design theory and realization for a programmable gain amplifier (PGA) with extremely small gain error and high-resolution decibel (dB)-linear characteristic in a 48 dB gain control range. Based on the resistive ladder attenuator topology and the complementary binary-weighted switching technique, the gain error in digitally controlled dB-linear characteristic is significantly reduced by introducing an optimization factor in the pseudo-exponential function fitting. To achieve both extremely small gain error and a relatively wide gain range, an optimization method for trading off different types of gain error is employed to obtain the optimal optimization factor. An adaptive bias circuit is adopted to realize gain robustness to process and temperature variations.The proposed PGA is fabricated in a 0.18 $\mu$ m CMOS technology with a 0.063 mm $^{2}$ core area. The power consumption is 5.3 mW at a supply voltage of 1.8 V. It provides a dB-linear gain range from $-$ 20 dB to 28 dB with a 0.86 dB gain step while the gain error is less than 0.06 dB. The PGA exhibits a $-$ 3 dB bandwidth of 80 MHz in various digital control words. The measured input 1-dB compression point is from $-$ 27.7 to 13 dBm, and the noise figure is from 13.4 to 62.5 dB.

In low intermediate frequency (low-IF) receivers, image interference rejection is one of the core tasks to be accomplished. Conventional active polyphase filters (APPFs) are unable to have a sufficient image rejection ratio (IRR) at high operating frequencies due to the degradation of the IRR by the amplitude and phase imbalances produced by the secondary pole. The proposed solution to the above problem is a frequency-dependent image rejection enhancement technique based on secondary pole compensation. By adjusting the dominant pole frequency of the high-pass filter (HPF) appropriately, the proposed technique can theoretically completely reject the image interference signal even in the presence of the secondary pole. The proposed APPF is simulated and fabricated in a 180-nm CMOS process. The simulation results show that the proposed technique can improve the IRR of the APPF by more than 30 dB at the operating frequency of hundreds of MHz. The measured IRR is better than −31 dB at the frequency from 95 to 105 MHz. Unlike conventional schemes, the proposed design is from the perspective of frequency correlation, which makes the operating frequency no longer limited by the secondary pole frequency. In addition, the proposed design also has an excellent IRR for quadrature input signals with phase imbalance.

Driven by the stringent demands of Internet of Things (IoT) applications, extended battery life and robust temperature stability have become key design metrics for navigation and positioning chips. This article presents a low-power fractional-N phase-locked loop (PLL) with temperature compensation for navigation and positioning applications. The proposed PLL integrates a temperature-adaptive dual-loop Class-C voltage-controlled oscillator (VCO). Benefiting from the high current efficiency and reduced temperature sensitivity of the proposed dual-loop VCO, the PLL simultaneously achieves low-power consumption, stable frequency generation, and low-phase noise (PN) over a wide temperature range. Fabricated in a 0.13- $\mu $ m CMOS process, the PLL consumes 5.6 mW from a 1.2 V supply. Measurement results over a temperature range of $- 40~^{\circ }$ C to $125~^{\circ }$ C demonstrate that the proposed PLL achieves an average frequency temperature coefficient (TC) of 0.72 ppm/°C. In addition, the PN variation remains below 0.3 dBc/Hz at a 100-kHz offset and 0.8 dBc/Hz at a 1-MHz offset.