YunQi Deng

Mr. YunQi Deng

orcid

Research Focus & Metrics

Academic Career Length

3Years (2024-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
3 August 2024 in Electronics
Verified
Journal Article
Open access
PDF file
YDYunQi Deng
YunQi Deng
PYPing Yang
Ping Yang
HGHuang Guangming
Huang Guangming
JLJun Liu
Jun Liu
ZRZhongguang Ren
Zhongguang Ren
ZSZixuan Song
Zixuan Song
The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB.

1 April 2026 in Journal of Instrumentation
Verified
Journal Article
Open access
CWC. Wang
C. Wang
XLXiaoting Li
Xiaoting Li
YBY. Bai
Y. Bai
HCH. Chen
H. Chen
JCJ. Chen
J. Chen
QZQ. Zhu
Q. Zhu
LATRIC0 is a single-channel readout chip designed for the Outer Tracker (OTK) of the reference detector on the Circular Electron Positron Collider (CEPC). The OTK employs AC-coupled Low-Gain Avalanche Detector (AC-LGAD) microstrip sensors to achieve high-precision spatial (10 µm) and timing (50 ps) measurements. Fabricated using a 55 nm CMOS process, LATRIC0 integrates an analog front-end amplifier and an event-driven ring-oscillator-based Time-to-Digital Converter (TDC) in a compact architecture. Measurements show that the prototype achieves a Least Significant Bit (LSB) of approximately 30 ps from both Time-over-Threshold (TOT) and Time-of-Arrival (TOA). The TDC core consumes less than 1.0 mW, while the total power of the front-end and TDC together is below 7.0 mW. The measured Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) are within 1 LSB. LATRIC0 not only validates the proposed timing architecture but also establishes a foundation for the development of a future fully functional version with 128 channels and 100-µm channel pitch.

20 April 2026 in Microelectronics Journal
Verified
Journal Article
Closed access
YDYunQi Deng
YunQi Deng
ZYZhuang Yue
Zhuang Yue
BXBinQiang Xiong
BinQiang Xiong
GHGuangMing Huang
GuangMing Huang
HPHua Pei
Hua Pei
PYPing Yang
Ping Yang

8 July 2026 in Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Verified
Journal Article
Closed access
YDYunQi Deng
YunQi Deng
ZSZhitao Song
Zhitao Song
YXYudong Xu
Yudong Xu
FYFangyuan Yan
Fangyuan Yan
XWXianzhen Wang
Xianzhen Wang
PYPing Yang
Ping Yang