As CMOS technology continues to downsize to the nanometer range, the exponential growth predicted by Moore’s Law has been significantly decelerated. Doubling chip density in the two-dimensional domain will no longer be feasible without further device downsizing. Meanwhile, emerging new device technologies, which may be incompatible with the mainstream CMOS technology, offer potential performance enhancements for system integration and could be options for a More-than-Moore system. Additionally, the explosive growth of artificial intelligence (AI) demands ever-high computing power and energy-efficient computing platforms. Heterogeneous multi-chip integration, which combines diverse components or a larger number of functional blocks with different process technologies and materials into compact 3D systems, has emerged as a critical pathway to overcome the performance limitations of monolithic integrated circuits (ICs), such as limited process/material options, low yield, and multifunctional design complexity. Furthermore, it sustains Moore’s Law progression for a further smaller footprint and higher integration density, and it has become pivotal for “More-than-Moore” strategies in the next CMOS technology revolution. This approach is also crucial for sustaining computational advancements with low-power dissipation and low-latency interconnects in the coming decades. The key techniques for heterogeneous wafer-to-wafer bonding involve both copper-to-copper (Cu-Cu) and dielectric-to-dielectric bonding. This review provides a comprehensive comparison of recent advancements in Cu-Cu bonding techniques. Major issues, such as plasma treatment to activate bonding surfaces, passivation to suppress oxidation, Cu geometry, and microstructure optimization to enhance interface diffusion and regrowth, and the use of polymers as dielectrics to mitigate contamination and wafer warpage, as well as pitch size scaling, are discussed in detail.

Contact scaling is a major challenge in nano complementary metal–oxide–semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current–voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts’ characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted.

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing.

Interface-passivated graphene/silicon Schottky junction solar cells have demonstrated promising features with improved stability and power conversion efficiency (PCE). However, there are some misunderstandings in the literature regarding some of the working mechanisms and the impacts of the silicon/insulator interface. Specifically, attributing performance improvement to oxygen vacancies and characterizing performance using Schottky barrier height and ideality factor might not be the most accurate or appropriate. This work uses Al₂O₃ as an example to provide a detailed discussion on the interface ALD growth of Al₂O₃ on silicon and its impact on graphene electrode metal–insulator–semiconductor (MIS) solar cells. We further suggest that the current conduction in MIS solar cells with an insulating layer of 2 to 3 nm thickness is better described by direct tunneling, Poole–Frenkel emission, and Fowler–Nordheim tunneling, as the junction voltage sweeps from negative to a larger forward bias. The dielectric film thickness, its band offset with Si, and the interface roughness, are key factors to consider for process optimization.

By embedding an aluminum-laminated layer within La₂O₃ thin films and subjecting them to high-temperature rapid thermal annealing, a La₂O₃/LaAl_xO_y/La₂O₃ sandwich dielectric was formed. This structure enhances the interface properties with both the silicon substrate and the metal gate electrode, improving current conduction. Comprehensive analysis using X-ray Photoelectron Spectroscopy (XPS) revealed that this novel process not only facilitates the formation of a high-quality lanthanum aluminate layer, as indicated with Al 2p peak at 74.5 eV, but also effectively suppresses silicate layer growth, as supported by the weak Si-O signal from both the Si 2s (153.9 eV) and O 1s (533 eV) peaks at the dielectric/Si interface in the Al-laminated samples. Fourier Transform Infrared (FTIR) spectroscopy revealed a significant reduction in the OH absorption peak at 3608 cm⁻¹ OH-related band centered at 3433 cm⁻¹. These improvements are attributed to the aluminum-laminated layer, which blocks oxygen and hydroxyl diffusion, the LaAl_xO_y layer scavenging interface silicon oxide, and the consumption of oxygen during LaAl_xO_y formation under thermal annealing. Electrical measurements confirmed that the dielectric films exhibited significantly lower interface and oxide trap densities compared to native La₂O₃ samples. This approach provides a promising method for fabricating high-quality lanthanum-based gate dielectric films with controlled dielectric/substrate interactions, making it suitable for nano-CMOS and memristive device applications.