A parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated. The concept referred to as the cross-switch (XS) hybrid aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties due to the combination of both the bipolar Si IGBT and unipolar SiC MOSFET characteristics. For the purpose of demonstrating the XS hybrid, the parallel configuration is implemented experimentally in a single package for devices rated at 1200 V. Test results are obtained to validate this approach with respect to the static and dynamic performance when compared to a full Si IGBT and a full SiC MOSFET reference devices having the same power ratings as for the XS hybrid samples.

In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si _0.5 Ge _0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, L _g , and ON-current, I _ON , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.

The cross hybrid (XS) concept has been demonstrated experimentally with 3.3-kV Si Insulated Gate Bipolar Transistor (IGBTs) and SiC MOSFETs in parallel, and used to calibrate 2D Technology Computer Aided Design simulations. The XS hybrid offers lower switching losses compared with full Si IGBTs and reduced oscillations compared with full SiC MOSFETs. The current sharing mechanism between the IGBT and the MOSFET in the XS hybrid has been elucidated, showing that under typical switching conditions, the IGBT dissipate 98% of the XS hybrid turn-OFF losses compared with the SiC MOSFET. Since the current density of the IGBT in the XS hybrid is twice of that of the full IGBT solution, it exhibits higher dynamic avalanche. These features results in stress at device and package level, thereby compromising robustness and reliability. In order to overcome such issues, we show that increasing the turn-OFF gate resistance improves current sharing in the XS hybrid by delaying the turn-OFF of the MOSFET, and thereby suppressing dynamic avalanche in the IGBT.

We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.