This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the critical path and to improve the clock frequency. A dedicated controller is implemented to provide control functionalities. For the performance evaluation of our design, we report implementation results for two different cases on Xilinx 7-series FPGA devices. For our case one, the proposed architecture can operate on 382, 379, and 388 MHz frequencies for Kintex-7, Virtex-7, and Artix-7 devices. On the same Kintex-7, Virtex-7, and Artix-7 devices, the utilized Slices are 49, 51, and 50. For one encryption and decryption computation, our design takes 16 clock cycles. The minimum power consumption is 172 mW on the Kintex-7 device. For the second case, we targeted the same circuit frequency of 50 MHz for synthesis on Kintex-7, Virtex-7, and Artix-7 devices. With minimum hardware resource utilization (51 Slices), the least consumed power of 13.203 mW is obtained for the Kintex-7 device. For proof-of-concept, the proposed SIMECK design is validated on the NEXYS 4 FPGA with the Artix-7 device. Consequently, the implementation results reveal that the proposed architecture is suitable for many resource-constrained cryptographic applications.

The Internet of Things (IoT), which is characteristic of the current industrial revolutions, is the connection of physical devices through different protocols and sensors to share information. Even though the IoT provides revolutionary opportunities, its connection to the current Internet for smart cities brings new opportunities for security threats, especially with the appearance of new threats like quantum computing. Current approaches to protect IoT data are not immune to quantum attacks and are not designed to offer the best data management for smart city applications. Thus, post-quantum cryptography (PQC), which is still in its research stage, aims to solve these problems. To this end, this research introduces the Dynamic Galois Reed–Solomon with Quantum Resilience (DGRS-QR) system to improve the secure management and communication of data in IoT smart cities. The data preprocessing includes K-Nearest Neighbors (KNN) and min–max normalization and then applying the Galois Field Adaptive Expansion (GFAE). Optimization of the quantum-resistant keys is accomplished by applying Artificial Bee Colony (ABC) and Moth Flame Optimization (MFO) algorithms. Also, role-based access control provides strong cloud data security, and quantum resistance is maintained by refreshing keys every five minutes of the active session. For error correction, Reed–Solomon (RS) codes are used which provide data reliability. Data management is performed using an attention-based Bidirectional Long Short-Term Memory (Att-Bi-LSTM) model with skip connections to provide optimized city management. The proposed approach was evaluated using key performance metrics: a key generation time of 2.34 s, encryption time of 4.56 s, decryption time of 3.56 s, PSNR of 33 dB, and SSIM of 0.99. The results show that the proposed system is capable of protecting IoT data from quantum threats while also ensuring optimal data management and processing.

The protection of confidential information is a worldwide challenge, and block ciphers are the most reliable option by which data security is accomplished. To the best of our knowledge, this type of research is being performed for the first time, unlocking new avenues for block cipher design research, shifting the paradigm from cryptographer-designed ciphers to computationally generated. We propose a computational model named Block Cipher Design Generation Model (BCDGM) to generate a complete design of novel block ciphers and their primitives, such as cipher structures, S-boxes, inverse S-boxes, P-boxes, round functions, half-round functions, and derived keys, in an automated manner without the participation of cryptographers. To accomplish this goal, BCDGM only requires high-quality quantum random bits as input to generate a myriad of new block ciphers. A quantum circuit is designed over the International Business Machines Corporation (IBM) Quantum Santiago computer to generate high-quality random bits. BCDGM itself and all its generated cipher structures and primitives are invariably transparent, unreproducible, and nondeterministic due to their sole reliance on quantum random bits. Furthermore, every decision made by BCDGM is randomized. As a result, potential vulnerabilities and attacks that exist in other ciphers are bypassed in BCDGM-generated ciphers. Extensive experimentation was conducted, generating more than fifty thousand new block cipher designs tested over 107 terabytes of data. Generated ciphers are compared with twelve reputable standard block ciphers, including five AES competition finalists. The results show that the proposed block ciphers occasionally surpass standard ciphers and achieve equivalent security strength in many cases. The implementation of the proposed model is publicly available.