This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.

This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45 nm,for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell and pad library with the necessary support files to enable full chip place and route and verification for System on Chip designs. Test chips designed with this PDK are designed in such a way so that they can be fabricated by fabrication facilities allowing validation of the design rules so that the rules may be used in future multi-project runs and design contests.

A tunable third-order combline bandpass filter using thin-film barium-strontium-titanate varactors and fabricated on a sapphire substrate is reported. Application of 0-200-V bias varied the center frequency of the filter from 2.44 to 2.88 GHz (16% tuning) while achieving a 1-dB bandwidth of 400 MHz. The insertion loss varied from 5.1 dB at zero bias to 3.3 dB at full bias, while the return loss exceeded 13 dB over the range. The third-order intercept of the filter was found to be 41 dBm.

As the dominating CMOS technology is fast approaching a "brick wall," new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.

ABSTRACT:  Radio frequency identification (RFID) is an alternative technology with a potential to replace traditional universal product code (UPC) barcodes. RFID enables identification of an object from a distance without requiring a line of sight. RFID tags can also incorporate additional data such as details of product and manufacturer and can transmit measured environmental factors such as temperature and relative humidity. This article presents key concepts and terminology related to RFID technology and its applications in the food industry. Components and working principles of an RFID system are described. Numerous applications of RFID technology in the food industry (supply chain management, temperature monitoring of foods, and ensuring food safety) are discussed. Challenges in implementation of RFID technology are also discussed in terms of read range, read accuracy, nonuniform standards, cost, recycling issues, privacy, and security concerns.