Multilevel inverters are becoming more and more popular in photovoltaic applications because of lower total harmonic distortion, lower switching stress and lower electromagnetic interference. In this article, a single-phase five-level transformer-less PV inverter is proposed for the purpose of leakage current reduction. The inverter is based on a flying capacitor (FC) configuration, the voltages of FCs are balanced at V _dc /4 through the coordination of the two half-bridge at the switching frequency, helps to reduce investment cost in passive elements. Two bidirectional circuits are added to guarantee a constant common-mode (CM) voltage. The leakage current elimination mechanism is analyzed in detail with operational states and CM equivalent model. The losses are analyzed, the control strategy and the FCs are detailed designed. A comparison is also made in terms of the number of elements, voltage stress and CM voltage. Experiment results under grid-connected condition show that the proposed topology achieves both excellent differential-mode and CM performance.

The single-phase five-level transformer-less inverters have been gradually applied in photovoltaic (PV) grid-connected systems due to low voltage stress and excellent waveform quality. However, they also suffer from serious leakage current as conventional three-level inverters. In order to reduce the leakage current, a single-phase five-level transformer-less inverter is proposed in this paper. The proposed inverter guarantees the common-mode (CM) voltage is clamped to a half of the dc-link voltage when outputting ${\pm V_{dc}/2}$ and zero voltage levels. Consequently, the high-frequent CM voltage is avoided and the leakage current is suppressed. The voltage stresses of eight switches and two flying capacitors are only Vdc/4, thus the system investment cost and total losses are reduced. The conduction and switching losses are analyzed detailly and a comparison with some existing topologies is also made. Finally, the simulations and experiment are carried out based on a 1 kW prototype. The results show that the proposed single-phase five-level inverter can obtain both excellent differential-mode (DM) and CM performance.

The bridge arms of traditional three-phase multilevel converters are independent of each other; thus, more active switches and passive diodes are required. In order to reduce the number of devices, a coupled three-phase converter architecture, which is suitable for both dc-ac and ac-dc converters, is presented. Based on this architecture, a ten-switch three-phase three-level (10S-3P-3L) inverter is proposed in this article. The proposed topology employs only ten active switches and no additional diodes, which helps to cut size, weight, and costs of system. The proposed space vector modulation enables 10S-3P-3L inverter to operate full modulation indexes. A comparison between the proposed inverter with some existing topologies in terms of device voltage and current stresses, conduction loss, switching loss, and other parameters is made to highlight its excellent performance. Moreover, the experimental results from a 3-kW experimental prototype reveal that the proposed inverter offers superior power quality.

Multilevel inverter are popular solutions in photovoltaic power station, wind farm, and other renewable energy generation. This article presents a three-phase five-level inverter with high dc voltage utilization. A significant feature of the inverter is that its maximum dc voltage utilization is twice that of the traditional three-phase inverters such as neutral point clamped, flying capacitor (FC), cascaded H-bridge, and active NPC. What is more, the inverter can realize the self-starting and self-balancing of the FC, and the self-balancing of the dc-link capacitors, so the complex FC voltage balancing strategy and bus midpoint voltage control method are not needed anymore. The voltage and current stresses analysis and the design guidelines of components are discussed in detail. A comparison with some existing topologies has also been made to highlight its performance. Taking one phase as an example, both the simulations and experiments are carried out to verify the validity of the proposed inverter and modulation strategy.

Ten-switch three-phase three-level inverter (TP-TLI) is receiving more attention owing to the reduced system cost compared to traditional TP-TLIs. However, it still faces serious neutral-point voltage (NPV) balance problems. This article proposes a novel virtual space vector modulation (NVSVM) with optimized neutral-point voltage control (NPVC) capability. A set of virtual vectors are selected to generate zero NP current. By analyzing the vector synthesis principle over the full modulation areas, a new control degree, which is utilized to optimize the NPVC capability and reduce line voltage total harmonic distortion (THD), is introduced. Besides, a dead time compensation method based on volt–second balance is also given to reduce the switching loss. The NVSVM not only improves the NPVC capability without dc offset and obvious ac oscillations in NPV under the full range of modulation index and power factor conditions but also reduces line voltage THD and the switching loss. Theoretical analysis shows that the available NP current for the proposed NVSVM is about 2.75 times greater at most than that for traditional VSVM. Simulation and experimental results are given to validate the effectiveness of the NVSVM and control strategies.

Space vector pulsewidth modulation (SVPWM) provides enhanced performance for the coupled ten-switch three-phase three-level inverter (TP-TLI). However, it suffers from high common-mode voltage (CMV) and unbalanced neutral-point voltage (NPV). To solve this problem, a CMVR_SVPWM with CMV reduction and NPV control (NPVC) is proposed in this article. By using suitable vectors with lower CMVs and sequences, the amplitude of CMV is suppressed to 50% of the previous strategies for ten-switch TP-TLI. A newly control degree is explored to regular the NPV through the two pairs of newly virtualized vectors in each sector. The dwell time of each selected vector is indirectly calculated to cooperate the NPVC with the CMVR_SVPWM. By enhancing the dwell time of the desired small vector, the NPV can be balanced while maintaining the almost same output quality. The dead-time effect is analyzed, and the resulting CMV spikes is eliminated by increasing the dwell time of the vector which is less than twice the compensation time. It preferentially attempts to eliminated the CMV spikes based on volt-second balance. This minimizes the effect of the proposed compensation method on output quality. A 3-kVA experimental prototype is built up to verify the feasibility and performance of the proposed CMVR_SVPWM.