In this letter, the AlGaN/GaN/graded-AlGaN:Si-doped/ GaN double channel (GDC-SI) high electronic mobility transistors (HEMTs) with high saturation current density and linearity have been reported for low voltage applications. Compared with the standard AlGaN/GaN/AlGaN/GaN double channel GaN (SDC) HEMTs, the GDC-SI HEMTs exhibited the higher saturation current, the broader and flatter transconductance profile, the lower transconductance ( g _m ) derivatives, and lower on-resistance ( R _on ). Due to the Si-doped graded bottom barrier present in GDC-SI HEMTs, the profile of current gain cutoff frequency ( f _T ) and the maximum oscillation frequency ( f _max ) were flatter with the bias voltage increased. The output power density of 0.75 W/mm and power added efficiency (PAE) of 58% were achieved for GDC-SI HEMTs, at the drain voltage of 7 V and the test frequency of 3.6GHz. The output third-order intercept point (OIP3) of 39.3 dBm and saturation current density of 1909 mA/mm are achieved, which are the state-of-the-art saturation current and OIP3 in the double-channel GaN HEMTs.

In this letter, we apply an oxidation technique for p-GaN to a normally-off p-GaN/AlGaN/GaN HEMT to improve the threshold voltage and gate reliability. Oxygen-plasma and low-temperature Oxygen post-annealing treatment (OPAT) of p-GaN before the deposition of gate metal has introduced a 5 nm oxidation interlayer, resulting in a significant improvement in gate breakdown voltage, from 10.4 V to 20.6 V. Thanks to this interlayer, the threshold voltage of p-GaN gate HEMTs is increased from 1.9 V to 4.6 V, while an almost same on-state resistance and a higher drain breakdown voltage are obtained. Time-dependent gate breakdown measurement shows OPAT-HEMTs have a maximum on-state gate drive voltage of 9.2 V for a 10-year lifetime with a 63 % gate failure rate. In addition, a more stable threshold voltage under gate stress indicates the promising application of this technology in GaN power devices.

In this article, the superior power performance of a double-channel high-electron-mobility transistor (HEMT) operating at a high drain voltage of sub-6 GHz was demonstrated using a heterostructure of Al $_{\text{0}.\text{3}}$ Ga $_{\text{0}.\text{7}}$ N/GaN/Al $_{\textit{x}}$ Ga $_{\text{1}-\textit{x}}$ N/GaN, $\textit{x}$ ranging from 0.3 to 0, top-down double channel with graded barrier HEMT (DCGB-HEMT). In comparison to single channel HEMT (SC-HEMT), DCGB-HEMT exhibits superior direct current (dc) characteristics, including a wider gate voltage swing, a higher saturation current (up to 1307.80 mA/mm), and a higher OFF-state breakdown voltage (up to 165 V). Through TCAD simulation, the breakdown voltage was increased because the graded barrier reduces the peak value of the electric field at the gate’s edge on the drain side. Compared to SC-HEMT, DCGB-HEMT’s current collapse (CC) decreased from 23.35% to 9.82%. Electrons from the upper channel are more effectively prevented from being captured by acceptors in a buffer induced by Fe-doping by a thicker 3-D electron gas (3DEG) forming between the bottom channel and graded bottom barrier, prevailing over a thinner 2-D electron gas (2DEG). DCGB-HEMT’s maximum power-added efficiency (PAE) increased from 56% to 70.4%. DCGB-HEMTs exhibit superior PAE due to their improved gate control, lower leakage, and improved CC at high drain voltage.

In this work, the performance of AlGaN/ gallium nitride (GaN) high-electron mobility transistors (HEMTs) with different Fe doping tails was systematically investigated and compared. It is illustrated that the combination of the unintentionally doped (UID) GaN layer and a thinner Fe doping buffer layer would result in a faster slope rate of Fe concentration in the UID GaN layer. The devices with the fastest slope rate of Fe concentration in the UID GaN layer exhibited excellent large signal performance, including the saturated power density ( ${P}_{sat}$ ) of 9 W/mm and the power-added efficiency (PAE) of 65.6%. In addition, the ${P}_{sat}$ and the PAE of the device with the fastest slope rate of Fe concentration in UID GaN layer are 27.7% and 14.7%, which are higher than that of the device with the slowest slope rate of Fe concentration under the class AB operation conditions. Pulse ${I}$ ,– ${V}$ measurement results demonstrated that the buffer-related current collapse was more effectively suppressed in the 0.5- $\mu \text{m}$ Fe doping buffer layer because of faster slope rate of Fe concentration in UID GaN layer. Moreover, the frequency-dependent capacitance and conductance measurement results indicated that the current collapse was relevant to deep traps in the UID GaN layer introduced by Fe doping. By reducing the concentration of the deep traps caused by Fe doping, the device showed excellent characteristics of dc and RF. Furthermore, controlling the Fe doping tail was important for designing the GaN-based power amplifier with high ${P}_{sat}$ and PAE.

In this work, a high performance GaN-on-Si quasi vertical PiN diode was demonstrated by the combination of a beveled sidewall and self-aligned fluorine plasma treatment. The didoes achieved a remarkable breakdown voltage ( $\text{V}_{\text {BR}}{)}$ of 930 V and an ultra-low reverse leakage current. Meanwhile the didoes showed a low specific on-resistance ( $\text{R}_{ \mathrm{\scriptscriptstyle ON},\textit {sp}}$ ) of 0.43 $\text{m}\Omega \cdot $ cm ² , a high on/off current ratio ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of $10^{{11}}$ , and an excellent Baliga’s figure of merit (BFOM) of 2.01 GW/cm ² . The measurement results of X-ray spectroscopy (XPS) and Kelvin Probe Force Microscopy (KPFM) proved the presence of F ions and the decrease of surface potential, which reduced the electric field peak and suppressed the leakage current. These results show a great potential of GaN on Si PiN diode for power applications.

Low-damage plasma oxidation treatment for AlN/GaN high-electron-mobility transistors (HEMTs) was developed in this letter, with which high-performance enhancement-mode (E-mode) AlON/AlN/GaN HEMTs were demonstrated. After removal of in situ SiN cap layer within gate area, remote plasma oxidation (RPO) treatment of 4.9nm AlN barrier layer at 300 °C leads to formation of AlON insulator layer and effective depletion of 2-D electron gas channel, without etch-induced damage or serious interfacial issues compared with the commonly used gate- recess metal-insulator-semiconductor HEMTs. Thanks to the low-damage RPO treatment, the achieved E-mode HEMTs with threshold voltage of 0.4 V exhibit quite a small loss of output current (7.8%) compared with the depletion-mode devices. In addition, the AlON gate insulator layer results in a remarkable increase in breakdown voltage of devices from 20 V to 74 V, which benefits the high-voltage operation of AlN/GaN technology. Further investigation shows that the oxidation process of AlN barrier tends to be saturated with treatment time increasing, providing a promising solution to the high-performance E-mode operation of scaled GaN-based HEMTs in RF applications.