The utilization of wide band-gap semiconductor devices provides the possibility of higher switching frequency and power density for power converters. However, the influence of parasitic parameters becomes more significant. It deteriorates the converter performance and leads to extra loss. In this paper, the extra loss caused by the parasitic capacitance of printed circuit boards (PCBs) is studied. The mechanism is explained, and the model of full-bridge topology with PCB parasitic capacitance is proposed as an example. Both the capacitance in power loops and control circuits are considered in the proposed model. Besides the capacitive loss in power loops, losses are also introduced by the capacitive coupling between the power and control circuits due to the potential pulsation of the control ground. This potential pulsation is analyzed and the calculation method of corresponding losses is presented. The formation of PCB parasitic capacitance is analyzed detailedly and corresponding layout optimization methods are proposed. Theoretical analyses are verified on a GaN-based full-bridge prototype with calorimetric loss measurement. The comparison of calculated and measured losses is presented, which shows a switching loss deviation of 26% without the consideration of parasitic capacitance and a 40% reduction on the extra losses after the proposed optimization.

Wide bandgap semiconductors with fast switching speed capability are becoming an enabler to achieve the higher-power density design. However, the further increase of switching frequency cannot continuously improve the power quality of ac-side waveforms in dc-ac/ac-dc application. The main reason is the distortion of PWM voltage at switching point under high switching frequency. In general, there are two contributors causing PWM voltage distortion in bridge-based topologies. One is the deadtime, which occupies higher ratio in the small duty cycle case under high switching frequency and induces the voltage error. The other one is the turn-off transient in the small load current or around the zero-crossing point of the ac-side current, because the relatively slow rising slope of the drain voltage will affect the right duty cycle. To solve this issue, the paper proposes a closed-loop modulation scheme to compensate the duty cycle distortion of PWM-voltage based on one-cycle control or charge control. Compared to the traditional feedforward-type of compensation, the proposed scheme does not need online calculation and instantaneous inductor current sampling. Simulations and experiments are carried out on a 400 kHz single phase full bridge inverter with 400 Hz fundamental frequency to demonstrate the performance of the proposed approach.

Due to the existence of predicting errors in the power systems, such as solar power, wind power and load demand, the economic performance of power systems can be weakened accordingly. In this paper, we propose an adaptive solar power forecasting (ASPF) method for precise solar power forecasting, which captures the characteristics of forecasting errors and revises the predictions accordingly by combining data clustering, variable selection, and neural network. The proposed ASPF is thus quite general, and does not require any specific original forecasting method. We first propose the framework of ASPF, featuring the data identification and data updating. We then present the applied improved k-means clustering, the least angular regression algorithm, and BPNN, followed by the realization of ASPF, which is shown to improve as more data collected. Simulation results show the effectiveness of the proposed ASPF based on the trace-driven data.

When multichannel light-emitting diode (LED) strings are applied in display backlight application, it's necessary to keep the brightness identical and adjustable. This paper deals with the capability of pulsewidth modulation dimming control method for capacitor-clamped current sharing circuit. By detecting the rising-edge of dimming pulse and turn on the switches of current sharing circuit in rotation, this method can achieve current sharing at any dimming frequency and dimming ratio. What is more, to improve the dynamic response of LED current and achieve a high dimming ratio, a control method based on the output voltage feedforward is proposed, which can decrease the rising time of the LED forward current significantly. The operational principle and parameter design are analyzed in detail. Based on this analysis, a three-string current sharing circuit driven by Buck converter is fabricated and tasted in the laboratory. Experimental waveforms demonstrate the validity.

In aircraft, the high dc component and even harmonics in the input current of the front-end Vienna rectifier during faults can easily trigger the generator to protect and interrupt the power supply. However, existing fault-tolerance control (FTC) methods cannot effectively reduce them. In this article, first, the impact of an open-circuit fault of a switch on the voltage vector is analyzed. The reason why existing FTC methods fail to improve the half-wave symmetry of input current (HWSIC) is also revealed. Then, a FTC method for improving the HWSIC is proposed. In this method, for areas affected by the fault, the offset voltages injected into the reference voltages are derived in detail. This involves accurately synthesizing the reference voltage vector (RVV) by replacing the infeasible vector with the redundant vector and approximately synthesizing RVV with only two available vectors. For areas unaffected by the fault, the offset voltages injected into the reference voltages are also discussed to achieve a completely symmetrical synthesis style of RVV in the positive and negative half-cycles of the current. As a result, good HWSIC can be obtained. Additionally, the total harmonic distortion of the input current and the ripple of the dc output voltage are reduced. Finally, the effectiveness of the proposed FTC method is verified through experiments.

It is crucial for the reliable operation of the Autotransformer rectifier unit (ATRU) to accurately diagnose diode open-circuit (OC) fault. However, grid voltage disturbance may lead to misdiagnosis by existing methods. This paper takes the 18-pulse ATRU as an example and firstly analyzes its sag-based fault feature in the dc-link output voltage (DLOV) caused by diode OC fault under no grid voltage disturbance. Then, the reason for misdiagnosis under grid voltage disturbance is discussed. Subsequently, a general diode OC fault diagnosis method with strong immunity to grid voltage disturbance is proposed. In the proposed method, the DLOV waveform is divided equally according to the number of rectified pulses. Hausdorff Distance (HD) algorithm is employed to extract the sag-based fault feature by calculating the similarity between the DLOV sampling sequence and the constructed template sequence. To be immune to grid voltage disturbance, the template sequence is adaptively generated as per the sampling sequence in each interval. Also, the generalized minimum failure mode is defined to normalize two sequences for good universality. With the help of the phase of grid single-phase voltage, OC faults can be detected and located according to the interval positions with the sag. Finally, simulation and experimental results confirm the strong immunity of the proposed method to grid voltage disturbance and its good universality to the different ATRUs.