This paper presents criteria, using simple integer arithmetic, to determine if a layout of a pair of devices broken into multiple, identical sections cancels the effect of nonlinear process gradients. These criteria allow quantification of 12 layout symmetries that can be leveraged to cancel specific process gradient components. “Dispersion,” the degree to which device segments are distributed throughout a layout, is also quantified in a simple and intuitive way, and used to identify which of multiple gradient canceling layouts is best. Techniques to construct maximally dispersive quadratic gradient canceling layouts with arbitrary numbers of rows and columns are presented.

This paper presents a compact model for metal oxide semiconductor (MOS) capacitors, based on a time-dependent solution for the surface potential. This enables modeling of the frequency dependence of MOS capacitors, which is not possible with existing compact models. The model is implemented in Verilog-A, and is verified against two-dimensional (2-D) numerical device simulations with DESSIS.

Over the past decades, the number of submitted articles that use numerical approaches for SPICE models or for characterization (extraction) of parameters of existing SPICE models has grown significantly. Many of those articles rely on synthetic data, generated either from technology computer-aided design (TCAD) or from physical SPICE model simulations; most do not model/fit measured data. Furthermore, those articles do not evaluate the physical correctness, smoothness/monotonicity, or asymptotic correctness of the approach they propose. That is sufficient for initial evaluation of proposed techniques. However, it does not prove that they are “industrial strength.” This article presents benchmarks/guidelines for the proposed artificial intelligence (AI)/machine learning (ML) SPICE modeling and characterization techniques to try to help them become practical and useful.

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, ``gate-as-input'' equivalent network for these capacitances. Areas of focus for the future model developments are also proposed.