A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

We investigated the effect of using a synthetic ferrimagnetic (SyF) free layer in MgO-based magnetic tunnel junctions (MTJs) on current-induced magnetization switching (CIMS), particularly for application to spin-transfer torque random access memory (SPRAM). The employed SyF free layer had a Co₄₀Fe₄₀B₂₀/Ru/Co₄₀Fe₄₀B₂₀and Co₂₀Fe₆₀B₂₀/Ru/Co₂₀Fe₆₀B₂₀structures, and the MTJs (100 times (150-300) nm²) were annealed at 300 ^degC. The use of SyF free layer resulted in low intrinsic critical current density (J _c0) without degrading the thermal-stability factor (E/k _B T, where E, k _B, and T are the energy potential, the Boltzmann constant, and temperature, respectively). When the two CoFeB layers of a strongly antiferromagnetically coupled SyF free layer had the same thickness, J _c0 was reduced to 2-4 times10⁶ A/cm². This low J _c0 may be due to the decreased effective volume under the large spin accumulation at the CoFeB/Ru. The E/k _B T was over 60, resulting in a retention time of over ten years and suppression of the write current dispersion for SPRAM. The use of the SyF free layer also resulted in a bistable (parallel/antiparallel) magnetization configuration at zero field, enabling the realization of CIMS without the need to apply external fields to compensate for the offset field.

This paper describes an investigation of cosmic-ray-induced multicell error behavior in SRAMs. A combination of device- and circuit-level simulation was used to show that a parasitic bipolar effect is responsible for such errors, and the underlying mechanism is what we call a battery effect. We have also demonstrated, for the first time, that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well taps (Nc). The results are used as the basis of an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multicell errors. The proposed guideline simply states that the allocation of memory cells to addresses should be based on consideration of the Nc. The architecture in its form reduces the soft error rate of an SRAM with Nc=16 by 88%.