In this study, we propose a “New Reliability Ratio Weighted Bit Flipping” (NRRWBF) algorithm for Low‐Density Parity‐Check (LDPC) codes. This algorithm improves the “Reliability Ratio Weighted Bit Flipping” (RRWBF) algorithm by modifying the reliability ratio. It surpasses the RRWBF in performance, reaching a 0.6 dB coding gain at a Binary Error Rate (BER) of 10⁻⁴ over the Additive White Gaussian Noise (AWGN) channel, and presents a significant reduction in the decoding complexity. Furthermore, we improved NRRWBF using the sum of the syndromes as a criterion to avoid the infinite loop. This will enable the decoder to attain a more efficient and effective decoding performance.

We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10⁻⁵ with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.

In this work, we introduce a novel decoding algorithm named “Reliability Ratio Weighted Bit Flipping–Sum Product” (RRWBFSP) is proposed for regular LDPC codes. “Sum Product” [4] and “Reliability Ratio Weighted Bit Flipping” [6] are two separate methods that are combined in the new algorithm. The simulations show novel algorithm to exceed Sum-Product decoding algorithms by 0.34 dB. In addition, when compared to the Sum-Product, the RRWBFSP approach has about the same computational complexity. Thus, LDPC codes, of which the “Double-Orthogonal Convolutional Recursive” (RCDO) subfamily is envisioned for use in electronic hard disks and mobile terminals, can be easily iteratively decoded. This would have the impact of prolonging the life of the batteries and consequently reducing the ecological footprint of the discarded batteries.

Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code ($280,176$) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of ${10}^{-2}$, the decoder outperforms the shorter reference codes ($60,40$) and ($96,64$), with an $E_b/N_0$ gain of up to $0.9$ dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of $218.62$ MHz, resulting in a throughput of $155.77$ Mbps, while maintaining a decoding latency of only $1.129$ µs and a power consumption of $0.201$ W.