The scheduling of data access plays a prominent part in a memory-based fast Fourier transform (FFT) processor. In this article, a conflict-free data-access scheme is proposed and applied to implement a radix-2^k FFT processor with the computing parallelism being the power of 2. The proposed FFT module exploits single-port RAMs to retain the area efficiency, and it has the following hardware-friendly features. First, the memories are merged into four banks under the arbitrary computing parallelism, which helps to circumvent the complicated data-routing circuit. Second, the parallelism of the input/output (I/O) data can be enlarged to the internal computing parallelism, which accelerates the data update and enhances the throughput capability. Furthermore, the concurrent I/O operation that overlaps the storage of the FFT input with the supply of FFT output in the same memory sets is allowed, which minimizes the memory occupation for the management of continuous data flow. Based on the testing on the field-programmable gate array (FPGA) and ASIC implementation using the SMIC 40-nm CMOS technology, it is demonstrated that the proposed FFT processor can offer high throughput and simultaneously achieve remarkable area and power efficiency.

A fully integrated passive ultrahigh-frequency (UHF) RF identification (RFID) tag integrated circuit (IC) based on Chinese UHF RFID standard (GJB 7377.1) is proposed. An optimized voltage multiplier with threshold compensation and leakage current suppression is designed to improve the RF-DC power conversion efficiency, which is more than 58% for different load current. A system clock constraint condition and proposed digital baseband (BB) algorithm instead of clock calibration is introduced to ensure correct demodulation of the forward link from reader to tag and back link frequency (BLF) tolerance from tag to reader. Moreover, a 2Kb multi-time programmable (MTP) non-volatile memory (NVM) in standard CMOS process without any additional masks and process modification is designed and implemented to significantly save the manufacture cost of the chip. The proposed RFID tag IC is fabricated using a 0.13-μ m one-poly-five-metal (1P5M) standard CMOS process with an area of 620x 660 μ m² and a power consumption of 4.8 μW and 11.5 μW for reading and writing operations, respectively. The tag with antenna gain of 2 dBi shows successful reading detection at distances up to 17 m in the case of 4 W Equivalent Isotropically Radiated Power (EIRP) from reader.

Digital multi-beam synthesis technology is generally used in the on-orbit satellite-based Automatic Dependent Surveillance–Broadcast (ADS-B) system. However, the probability of successfully detecting aircraft with uneven surface distribution is low. An adaptive digital beamforming method is proposed to improve the efficiency of aircraft detection probability. The current method has the problem of long operation time and is not suitable for on-orbit operation. Therefore, this paper proposes an adaptive beamforming method for the ADS-B system based on a fully connected neural network (FCNN). The simulation results show that the calculation time of this method is about 2.6 s when more than 15,000 sets of data are inputted, which is 15–80% better than the existing methods. Its detection success probability is 10% higher than those of existing methods, and it has better robustness against large amounts of data.

The development of space-based Internet of Things is limited by insufficient allocable frequency resources and low spectrum utilization. To meet the demand for massive access users under the condition of restricted frequency resources, a multi-dimensional hybrid multiple-access method for space-time-frequency-code division based on user distribution (MHSTFC-UD) is established. It divides the beam cell of a low orbit satellite into the central and edge area and dynamically adjusts the radius of the central area and the allocation of frequency resources according to the distribution of users. The optimization model for the radius of the central area and the allocation of frequency resources is established and solved by the genetic algorithm. Also, it takes the edge area as the protection interval to realize the full-frequency multiplexing between the beam cells in the time domain, space domain and code domain. The simulation results show that compared with the traditional method of frequency reuse in two or three dimensions, the multi-dimensional hybrid multiple-access method can improve the maximum access capacity of a single satellite user by one to three orders of magnitude. Moreover, the MHSTFC-UD can increase users by an additional 11.5% to 33.1% compared to fixed area division and frequency resource allocation.

This paper presents an ultra-low power RFID with an embedded CMOS temperature sensor. The thermometry working flow of the Query01-Query00-Ack sequence is introduced, which is compatible with the EPC GEN-2 standard. A 2k-bits multi-time programmable (MTP) non-volatile memory (NVM) array with standard CMOS process is used to store tag information, tag-identification (TID), electronic product code (EPC), initialization parameter and temperature sensor (TS) data. The proposed rectifier can achieve a wide power dynamic range (PDR) of 21.5 dB with peak power conversion efficiency (PCE) of 65%@-15 dBm under a 100kΩ load. A protection mechanism for reliable reading and writing is presented to ensure proper tag initialization and avoid the ghost tag phenomenon. Time domain digital quantization is adopted to convert the signal that period varies with temperature into a digital signal for low power consumption. The temperature sensor achieves a resolution of 0.16°C and inaccuracy of +0.42/-0.83 °C after one point calibration at 0 °C in the temperature range from -20 °C to 30 °C. When the temperature sensor is powered at 1 V, it can achieve 0.234 nJ of energy per conversion in a conversion time of 1.8ms. The passive RFID temperature sensor occupies an area of 0.5579 mm² in 0.13um CMOS process. At the frequency of ~910 MHz, measured tag sensitivity can reach -22 dBm and the 3 dB bandwidth is 51.5 MHz.

This paper presents a memory-reduced hardware architecture for acquiring the frequency of sinusoidal signal based on the interpolated discrete Fourier transform (IpDFT). By exploiting the sparsity of the sinusoidal signal in the frequency domain, a spectrum compression method that can remove the unnecessary spectral lines is proposed together with the corresponding parameter extraction scheme, which circumvents the large-point DFT computation involved in the conventional IpDFT and thereby reduces the memory consumption markedly. On this basis, a low-latency hardware architecture is designed for the proposed frequency estimator. Implementation results demonstrates the proposed work can gain satisfactory accuracy while retaining low hardware cost and latency.