Ultrasound (US) imaging is widely employed for diagnosis and staging of vascular diseases, mainly due to its high availability and the fact it does not emit ionizing radiation. However, high interoperator variability limits the repeatability of US image acquisition. To address this challenge, we propose an end-to-end workflow for automatic robotic US screening of tubular structures using only real-time US imaging feedback. First, a U-Net was trained for real-time segmentation of vascular structure from cross-sectional US images. Then, we represented the detected vascular structure as a 3-D point cloud, which was used to estimate the centerline of the target structure and its local radius by solving a constrained nonlinear optimization problem. Iterating the previous processes, the US probe was automatically aligned to the normal direction of the target structure, while the object was constantly maintained in the center of the US view. The real-time segmentation result was evaluated both on a phantom and in vivo on brachial arteries of volunteers. In addition, the whole process was validated using both simulation and physical phantoms. The mean absolute orientation, centering, and radius error ($\pm$ SD) on a gel phantom were $\text{3.7}\pm \text{1.6}^{\circ }$, $0.2\pm \text{0.2}\,\text{mm}$ and $0.8\pm \text{0.4}\,\text{mm}$, respectively. The results indicate that the method can automatically screen tubular structures with an optimal probe orientation (i.e., normal to the vessel) and accurately estimate the radius of the target structure.

The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one step further, partial dynamic self-reconfiguration becomes possible through the internal configuration access port (ICAP). In this paper a framework for lowering reconfiguration times using the combitgen tool to reduce the overhead found within bitstreams, along with a completely new, very simple and area efficient ICAP controller that is connected directly to the processor local bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the on-chip peripheral bus), it is possible to achieve improvements concerning reconfiguration times by a factor of 20.

Neuromorphic vision sensor is a new passive sensing modality and a frameless sensor with a number of advantages over traditional cameras. Instead of wastefully sending entire images at fixed frame rate, neuromorphic vision sensor only transmits the local pixel-level changes caused by the movement in a scene at the time they occur. This results in advantageous characteristics, in terms of low energy consumption, high dynamic range, sparse event stream, and low response latency, which can be very useful in intelligent perception systems for modern intelligent transportation system (ITS) that requires efficient wireless data communication and low power embedded computing resources. In this paper, we propose the first neuromorphic vision based multivehicle detection and tracking system in ITS. The performance of the system is evaluated with a dataset recorded by a neuromorphic vision sensor mounted on a highway bridge. We performed a preliminary multivehicle tracking-by-clustering study using three classical clustering approaches and four tracking approaches. Our experiment results indicate that, by making full use of the low latency and sparse event stream, we could easily integrate an online tracking-by-clustering system running at a high frame rate, which far exceeds the real-time capabilities of traditional frame-based cameras. If the accuracy is prioritized, the tracking task can also be performed robustly at a relatively high rate with different combinations of algorithms. We also provide our dataset and evaluation approaches serving as the first neuromorphic benchmark in ITS and hopefully can motivate further research on neuromorphic vision sensors for ITS solutions.

Driveable area detection is a key component for various applications in the field of autonomous driving (AD), such as ground-plane detection, obstacle detection and maneuver planning. Additionally, bulky and over-parameterized networks can be easily forgone and replaced with smaller networks for faster inference on embedded systems. The driveable area detection, posed as a two class segmentation task, can be efficiently modeled with slim binary networks. This paper proposes a novel binarized driveable area detection network (binary DAD-Net), which uses only binary weights and activations in the encoder, the bottleneck, and the decoder part. The latent space of the bottleneck is efficiently increased (×32→×16 downsampling) through binary dilated convolutions, learning more complex features. Along with automatically generated training data, the binary DAD-Net outperforms state-of-the-art semantic segmentation networks on public datasets. In comparison to a full-precision model, our approach has a ×14.3 reduced compute complexity on an FPGA and it requires only 0.9MB memory resources. Therefore, commodity SIMD-based AD-hardware is capable of accelerating the binary DAD-Net.

In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms a comparable software version running on an Intel Core2Duo E8400 core at 3.00 GHz and delivers almost the same execution time compared to an implementation of the Harris corner detector running on an Nvidia GeForce 8800 GTX GPU.

The efficient applications of Convolutional Neural Networks (CNNs) in automotive-rated and safety critical hardware-accelerators require an interplay of DNN design optimization, programming techniques and hardware resources. Ad-hoc pruning would result in irregular sparsity and compression leading in very inefficient real world applications. Therefore, the proposed methodology, called Dense-Sparse Convolution, makes use of the right balance between pruning regularity, quantization and the underlying vectorized hardware. Different word length compute units, e.g. CPU, are used for low latency inference of the spares CNNs. The proposed open source CPU-kernel scales along with the vector word length and the number of cores.