We review recent compact modeling solutions for Organic and Amorphous Oxide TFTs (OTFTs and AOS TFTs, respectively), which were developed, under the framework of the EU-funded project DOMINO, to address issues specifically connected to the physics of these devices. In particular, using different approaches, analytical equations were formulated to model the Density of States (DOS), different transport mechanisms, trapping/de-trapping, drain current, stress, capacitances, frequency dispersion and noise. The final TFT models were, after implementation in Verilog-A, validated by means of the design and simulation of test circuits.

We present a new complete capacitance model for the Amorphous Indium-Gallium-Zinc-Oxide (IGZO) Thin-Film-Transistor (TFT), valid in the above-threshold and subthreshold regime ((Fermi level in the tail and deep states, respectively). The parameters applied in the model are analytically extracted from the current–voltage characteristics of the devices, using a previously developed unified model and parameter extraction method. The good agreement between our capacitance model and 3D numerical TCAD simulations proves the validity of our work, which is expected to be useful for the optimization of fabrication processes and for the prospective estimation of the effect of process conditions on circuit performances.

In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.

This article presents an analytical model to reproduce the I-V characteristics of a double-gate (DG) amorphous indium-gallium-zinc oxide (a-IGZO) TFT with symmetric structure. This model for the above-threshold region is based on the gate voltage dependence of surface potential and potential at the center of the semiconductor layer, which are described by analytical expressions. Considering the densities of the free and localized carrier in the semiconductor, the total carrier density, which is equal to the effective carrier density, is calculated. The carrier mobility, calculated as the ratio between the free carrier and the effective carrier density, depends on the gate voltage as a power law with the power parameter ɣ different from zero, as it is typically represented for the amorphous TFT. The drain current model has only 13 model parameters and was validated with six different simulated transistor structures, as well as with an experimental device. A good coincidence of the modeled characteristics with both the simulated and experimental devices was obtained.